Patents by Inventor Kameran Azadet

Kameran Azadet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for multi-band digital pre-distortion using a canonical form with reduced dimension look-up table
    Publication number: 20220416823
    Abstract: A system and method for multi-band digital pre-distortion (DPD) for a non-linear system. The system includes a DPD circuitry configured to perform multi-band DPD on a multi-band input signal to compensate for a non-linearity of a non-linear system. The multi-band input signal includes input signals of multiple frequency bands and the DPD circuitry is configured to perform DPD on an input signal of each frequency band per frequency band. The DPD circuitry is configured to perform the DPD using a combination of a look-up table (LUT) that evaluates a non-linear function and computation of terms of a non-linear polynomial of one or more variables representing the input signals of multiple frequency bands. Both the non-linear function and the non-linear polynomial are in a reduced dimension lower than a dimension of the multi-band input signal.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventor: Kameran AZADET
  • Analog-to-digital converter system, transceiver, base station and mobile device
    Patent number: 11528182
    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: December 13, 2022
    Assignee: INTEL CORPORATION
    Inventors: Kameran Azadet, Martin Clara, Daniel Gruber, Christian Lindholm, Hundo Shin
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20220384956
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: May 2, 2022
    Publication date: December 1, 2022
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asi, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • DIGITAL-TO-ANALOG CONVERTER, DIGITAL-TO-ANALOG CONVERSION SYSTEM, ELECTRONIC SYSTEM, BASE STATION AND MOBILE DEVICE
    Publication number: 20220345148
    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.
    Type: Application
    Filed: December 23, 2019
    Publication date: October 27, 2022
    Inventors: Albert MOLINA, Kameran AZADET, Martin CLARA, Hundo SHIN
  • APPARATUS FOR CORRECTING A MISMATCH, DIGITAL-TO-ANALOG CONVERTER SYSTEM, TRANSMITTER, BASE STATION, MOBILE DEVICE AND METHOD FOR CORRECTING A MISMATCH
    Publication number: 20220345143
    Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The apparatus comprises an input configured to receive the digital input word. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits in order to generate first modified bits, and a second processing circuit for the second number of bits comprising a second filter configured to modify the second number of bits in order to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC.
    Type: Application
    Filed: December 27, 2019
    Publication date: October 27, 2022
    Inventors: Daniel GRUBER, Ramon SANCHEZ, Kameran AZADET, Martin CLARA
  • SEMICONDUCTOR CHIP PROVIDING ON-CHIP SELF-TESTING OF AN ANA-LOG-TO-DIGITAL CONVERTER IMPLEMENTED IN THE SEMICONDUCTOR CHIP
    Publication number: 20220345144
    Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.
    Type: Application
    Filed: December 23, 2019
    Publication date: October 27, 2022
    Inventors: Kameran AZADET, Martin CLARA, Daniel GRUBER, Albert MOLINA, Hundo SHIN
  • ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR CALIBRATING THE SAME, METHOD FOR CALIBRATING A PIPELINED ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION AND MOBILE DEVICE
    Publication number: 20220345146
    Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.
    Type: Application
    Filed: December 27, 2019
    Publication date: October 27, 2022
    Inventors: Albert MOLINA, Kameran AZADET, Martin CLARA, Matteo CAMPONESCHI, Christian LINDHOLM
  • DIGITAL-TO-ANALOG CONVERTER, DATA PROCESSING SYSTEM, BASE STATION, AND MOBILE DEVICE
    Publication number: 20220294462
    Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.
    Type: Application
    Filed: December 23, 2019
    Publication date: September 15, 2022
    Inventors: Daniel GRUBER, Kameran AZADET, Yu-Shan WANG, Hundo SHIN, Martin CLARA
  • Wireless communication technology, apparatuses, and methods
    Patent number: 11424539
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Apparatus for generating synchronized clock signals, elec-tronic system, base station and mobile device
    Patent number: 11378999
    Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Yu-Shan Wang, Martin Clara, Daniel Gruber, Hundo Shin, Kameran Azadet
  • VECTOR PROCESSOR SUPPORTING LINEAR INTERPOLATION ON MULTIPLE DIMENSIONS
    Publication number: 20220197640
    Abstract: Techniques are disclosed for a vector processor architecture that enables data interpolation in accordance with multiple dimensions, such as one-, two-, and three-dimensional linear interpolation. The vector processor architecture includes a vector processor and accompanying vector addressable memory that enable a simultaneous retrieval of multiple entries in the vector addressable memory to facilitate linear interpolation calculations. The vector processor architecture vastly increases the speed in which such calculations may occur compared to conventional processing architectures. Example implementations include the calculation of digital pre-distortion (DPD) coefficients for use with radio frequency (RF) transmitter chains to support multi-band applications.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Kameran Azadet, Joseph Williams, Zoran Zivkovic
  • Segmented digital-to-analog converter with subtractive dither
    Publication number: 20220200617
    Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and ?1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
    Type: Application
    Filed: November 17, 2021
    Publication date: June 23, 2022
    Inventors: Martin CLARA, Daniel GRUBER, Kameran AZADET
  • Method and apparatus for in-phase and quadrature imbalance correction in a frequency domain
    Publication number: 20220200838
    Abstract: An apparatus and method for in-phase/quadrature (I/Q) imbalance correction in a transceiver. The apparatus includes an I/Q imbalance correction circuit and a correction coefficient generation circuit. The I/Q imbalance correction circuit is configured to modify I/Q data in a frequency domain using correction coefficients to generate corrected I/Q data. The correction coefficient generation circuit is configured to generate the correction coefficients for the I/Q imbalance correction circuit based on the I/Q data and reference data.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Kameran AZADET, Marc Jan Georges TIEBOUT
  • PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
    Publication number: 20220197641
    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Kameran Azadet, Jeroen Leijten, Joseph Williams
  • Method and system for digital pre-distortion using look-up table
    Publication number: 20220200618
    Abstract: A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.
    Type: Application
    Filed: November 17, 2021
    Publication date: June 23, 2022
    Inventors: Ramon SANCHEZ, Kameran AZADET
  • METHOD AND SYSTEM FOR DIGITAL FEED-FORWARD LINEARIZATION
    Publication number: 20220200643
    Abstract: A method and system for digital feed-forward linearization. The system includes a main transmit path and an auxiliary transmit path. The main transmit path includes circuitries configured to process a transmit signal for transmission. The main transmit path includes a power amplifier (PA) for amplifying the transmit signal. The auxiliary transmit path includes circuitries configured to generate, in a digital domain, a distortion error signal corresponding to a distortion introduced to the transmit signal due to a non-linear characteristics of the PA in the main transmit path and convert the distortion error signal to an analog distortion error signal. The analog distortion error signal is combined with an output of the PA in the main transmit path. The auxiliary transmit path comprises a PA model circuit that mimics the behavior of the PA to generate a distorted transmit signal in a digital domain.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Ramon SANCHEZ, Kameran AZADET
  • Time-interleaved analog-to-digital converter system
    Patent number: 11271578
    Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet, Matteo Camponeschi, Jose Luis Ceballos, Christian Lindholm
  • Digital-to-analog conversion system
    Patent number: 11239866
    Abstract: A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 1, 2022
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Ramon Sanchez, Kameran Azadet, Martin Clara
  • ANALOG-TO-DIGITAL CONVERTER SYSTEM, TRANSCEIVER, BASE STATION AND MOBILE DEVICE
    Publication number: 20210385119
    Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 9, 2021
    Inventors: Kameran AZADET, Martin CLARA, Daniel GRUBER, Christian LINDHOLM, Hundo SHIN
  • TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER SYSTEM
    Publication number: 20210367607
    Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter- leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.
    Type: Application
    Filed: March 29, 2019
    Publication date: November 25, 2021
    Inventors: Albert MOLINA, Kameran AZADET, Matteo CAMPONESCHI, Jose Luis CEBALLOS, Christian LINDHOLM