Patents by Inventor Kameran Azadet

Kameran Azadet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10164800
    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet
  • Publication number: 20180287827
    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Albert Molina, Kameran Azadet
  • Patent number: 10044367
    Abstract: Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal xq; and apply noise shaping to the input signal xq to generate a noise shaped output signal yq, wherein an in-band noise of the noise shaped output signal yq is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal yq is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal yq in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Ramon Sanchez
  • Patent number: 9960900
    Abstract: Methods and apparatus are provided for modeling of a physical system using two-dimensional look-up tables.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Patent number: 9942078
    Abstract: Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: April 10, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Ramon Sanchez
  • Patent number: 9935761
    Abstract: Improved techniques are provided for modeling a target Volterra series using an orthogonal parallel Weiner decomposition. A target Volterra Series is modeled by obtaining the target Volterra Series V comprised of a plurality of terms up to degree K; providing a parallel Wiener decomposition representing the target Volterra Series V, wherein the parallel Wiener decomposition is comprised of a plurality of linear filters in series with at least one corresponding static non-linear function, wherein an input signal is applied to the plurality of linear filters and wherein outputs of the non-linear functions are linearly combined to produce an output of the parallel Wiener decomposition; computing a matrix C.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Patent number: 9923595
    Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet
  • Patent number: 9813223
    Abstract: Techniques for non-linear modeling of a physical system are provided using direct optimization of look-up table values. A non-linear system with memory is modeled by obtaining physical data for the non-linear system by applying a set of input samples x(n) to the non-linear system and measuring an output y(n) of the non-linear system; directly computing parameters ? of a memory model for the non-linear system from the physical data, wherein the memory model comprises one or more look-up tables having linear interpolation and wherein the parameters ? produce a substantially minimum mean square error; and providing the parameters ? for storage as entries in the one or more look-up tables. The mean square error can be determined, for example, using one or more of a least squares algorithm, a least mean square algorithm and a recursive least squares algorithm. The look-up tables are optionally used in a processor instruction to implement digital pre-distortion.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Patent number: 9813224
    Abstract: A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Publication number: 20170293485
    Abstract: Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 12, 2017
    Inventors: Kameran Azadet, Steven C. Pinault
  • Patent number: 9787459
    Abstract: Non-linear interference cancellation techniques are provided for wireless transceivers. Non-linear reduction of interference of a transmit signal on a received signal in a transceiver device, comprises applying the transmit signal to a first non-linear system; applying the received signal to a second non-linear system; and subtracting an output of the first non-linear system output from an output of second non-linear system output to produce an interference mitigated received signal. The first non-linear system and/or the second non-linear system can be implemented using one or more of a Volterra series and a Generalized Memory Polynomial Model. System parameters of the first non-linear system and/or the second non-linear system are adapted to reduce a power of the interference mitigated received signal.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Patent number: 9778902
    Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Chengzhou Li, Albert Molina, Joseph H. Othmer, Steven C. Pinault, Meng-Lin Yu, Joseph Williams, Ramon Sanchez Perez, Jian-Guo Chen
  • Patent number: 9760338
    Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Patent number: 9632750
    Abstract: Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Steven C. Pinault
  • Patent number: 9612794
    Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Joseph H. Othmer, Meng-Lin Yu
  • Patent number: 9602127
    Abstract: Devices and methods of reducing quantization noise using a pyramid stream encoder are generally described. Groups of D digital symbols are iteratively computed for a digital signal such that each group of symbols minimizes a norm of a weighted residue vector. The weighted residue vector is formed by applying predetermined weighting coefficients to components of a residue vector. Each component is a difference between a sample of the digital signal and a linear combination of different groups of digital symbols with predefined filter coefficients. The norm of the weighted residue vector evaluated at a rate D times slower than a sampling rate of an output signal. The groups of D digital symbols are provided as the output signal.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventor: Kameran Azadet
  • Patent number: 9529567
    Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Parakalan Venkataraghavan, Meng-Lin Yu, Joseph Williams
  • Publication number: 20160365950
    Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 15, 2016
    Inventor: Kameran Azadet
  • Publication number: 20160308577
    Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Albert MOLINA, Kameran Azadet
  • Patent number: 9372663
    Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: June 21, 2016
    Assignee: Intel Corporation
    Inventor: Kameran Azadet