Abstract: Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

Abstract: Multi-dimensional finite impulse response filters are disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (or matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

Abstract: A duobinary optical communication system is disclosed that employs pulse amplitude modulation (PAM) techniques to provide further improvements in spectral efficiency. A disclosed PAM duobinary optical transmitter converts a plurality of input bits to an N level signal using PAM techniques; adds a current N level signal to a previous N level signal to produce a 2N?1 level signal; and converts the 2N?1 level signal to an optical signal for transmission to a receiver. A disclosed PAM duobinary optical receiver detects a power level of the received optical signal (encoded using pulse amplitude modulation and duobinary encoding techniques to encode a plurality of bits) and maps the detected power level to a plurality of bits to return the transmitted information. An exemplary PAM-4 duobinary optical communication system combines PAM-4 modulation techniques with duobinary pulse shaping techniques to provide an overall factor of four improvement in spectral efficiency by reducing the bandwidth of the optical signal.

Abstract: Embodiments of the invention include an integrated circuit including a phase-locked loop (PLL). The integrated circuit includes a phase detector, a frequency detector, a loop filter, a digitally-controlled oscillator and a corresponding plurality of frequency dividers. The phase detector generates a first binary output based on a phase comparison of a reference clock signal to a plurality of clock phase inputs. The frequency detector generates a second binary output based on a frequency comparison of the reference clock signal to the clock phase inputs. The loop filter generates a third binary output based on the first binary output and the second binary output. The DCO feeds back the clock phase inputs, via the frequency dividers, to the phase detector based on the third binary output, and feeds back one of the clock phases to the frequency detector based on the third binary output.

Abstract: A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N?T.

Abstract: An amplitude modulated optical communication system and method are disclosed that achieve bandwidth compression by making use of an n level amplitude modulation scheme in one or more frequency bands. A soft decision decoder is disclosed that provides at least two soft slicing levels between each signal level in the multiple level transmission scheme to define an “uncertainty” region therebetween. The soft slicing levels are used to evaluate the reliability of a given bit assignment. In addition to assigning a digital value based on the received signal level, one or more soft bits are assigned indicating a “reliability” measure of the output code.

Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

Abstract: A virus detection mechanism is described in which virus detection is provided by a network integrated protection (NIP) adapter. The NIP adapter checks incoming media data prior to it being activated by a computing device. The NIP adapter operates independently of a host processor to receive information packets from a network. This attribute of independence allows NIP anti-virus (AV) techniques to be “always on” scanning incoming messages and data transfers. By being independent of but closely coupled to the host processor, complex detection techniques, such as using check summing or pattern matching, can be efficiently implemented on the NIP adapter without involving central processor resources and time consuming mass storage accesses. The NIP adapter may be further enhanced with a unique fading memory (FM) facility to allow for a flexible and economical implementation of polymorphic virus detection.

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA).

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes it possible to remove the branch metrics unit and decision-feedback unit from the feedback loop, thereby reducing the critical path. A set of multiplexers select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed that uses precomputation (look-ahead) to increase throughput, with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: A peripheral controller is provided for controlling communications with one or more peripheral devices. The peripheral controller includes a controller for controlling one or more peripheral devices; and a single interface to a shared memory device that stores configuration information for at least one of the one or more peripheral devices and additional code, such as boot ROM code. The shared memory device may be, for example, an EEPROM or a serial flash memory device. The controller and shared memory device may optionally communicate using a serial bus to further reduce the pin count. A memory controller maps the user addresses into non-overlapping physical addresses within the shared memory device.

Abstract: A method and apparatus are disclosed for power management of an electronic device. The present invention reduces power consumption of an electronic device that communicates over a network by selecting a transmission mode with reduced power consumption as the battery level gets lower. A disclosed power management process monitors the battery level of an electronic device and selects a transmission mode (e.g., a transmission rate) with a lower power consumption when the battery power level reaches one or more predefined threshold levels.

Abstract: An integrated controller is provided for controlling communications with a plurality of peripheral devices. The integrated controller includes a bus interface for processing communications with a processor; a switch for routing communications between the processor and one or more of the peripheral devices; and a plurality of controllers, where each of the controllers provide an interface to at least one peripheral device. The controllers include at least one PHY controller for a corresponding peripheral device that provides an electrical interface to a connection, such as a network connection. The controllers also include at least one MAC controller that stores and forwards packets to and from a network connection.

Abstract: A method and apparatus are disclosed for reducing noise, such as external noise, cross-talk and echo, in an unbalanced channel. A cross-talk canceller is disclosed that uses a multi-dimensional finite impulse response filter to process both the differential, d, and common-mode, c, components of a received signal. Recovery of the differential mode component of the received signal is improved by reducing the contribution of the common mode component. The common mode component of a received signal may be expressed, for example, as the average of two voltages or two current signals. The differential and common mode components of the received signal are equalized. The disclosed multi-dimensional cross-talk canceller reduces external noise; near-end crosstalk resulting from differential and common mode components on one twisted pair interfering with another twisted pair; and echo crosstalk resulting from differential and common mode cross-talk components on the same twisted pair.

Abstract: A single-sideband dense wavelength division multiplexing optical communication system and method are disclosed that achieve an increased throughput by moving the carrier wavelengths from the center of the corresponding channel band and suppressing one of the sidebands associated with each channel band. Most of the power is placed in the selected sideband and additional bandwidth is available to increase the throughput within the selected sideband. An electrical signal is modulated to provide a passband signal without low frequency components. The disclosed modulation scheme shifts the carrier wavelengths within the wavelength grid to provide additional bandwidth for the selected sideband in each channel band. Generally, the bandwidth (and thus, throughput) that is available to the selected sideband increases by a factor of two.

Abstract: A method and apparatus are disclosed for converting a signal between the analog and digital domains using frequency interleaving. The disclosed frequency interleaving techniques can be similarly applied to convert analog signals to the digital domain or vice-versa. An analog-to-digital converter decomposes the input broadband signal into N frequency bands that are separately sampled (quantized) before a Fourier transform is applied to convert the signal into the digital domain. Each of the frequency bands can be sampled in the corresponding narrow passband using narrow-band converters, such as passband Sigma-Delta converters, or can be returned to baseband prior to sampling. The various analog samples are then converted to the digital domain using an inverse Fourier transform, or another combining technique. Both sampling and analog-to-digital conversion can be performed at a speed that is N times slower than the input frequency.