Patents by Inventor Kameran Azadet

Kameran Azadet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120014426
    Abstract: Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.
    Type: Application
    Filed: March 31, 2009
    Publication date: January 19, 2012
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Patent number: 8095857
    Abstract: A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. In addition, the disclosed RSSE decoder compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: January 10, 2012
    Assignee: Agere Systems Inc.
    Inventors: Kameran Azadet, Erich Franz Haratsch
  • Publication number: 20110310944
    Abstract: A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy.
    Type: Application
    Filed: October 19, 2010
    Publication date: December 22, 2011
    Inventors: SAMER HIJAZI, KAMERAN AZADET, MENG-LIN YU, JOSEPH OTHMER, RAMON SANCHEZ PEREZ
  • Publication number: 20110243281
    Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 6, 2011
    Applicant: AGERE SYSTEMS INC.
    Inventors: Erich F. Haratsch, Kameran Azadet
  • Patent number: 8015226
    Abstract: Methods and apparatus are provided for performing reduced complexity discrete Fourier transforms using interpolation An input sequence of length N is transformed by extending the input sequence to an extended input sequence of length M, where M is greater than N (a power of two greater than N); performing a discrete Fourier Transform (DFT), such as a power-of-two DFT, on the extended input sequence to obtain an interpolated sequence; and applying a conversion matrix to the interpolated sequence to obtain a DFT output for the input sequence of length N. The input sequence of length N can be extended to an extended input sequence of length M, for example, by employing a zero padding technique, a cyclic extension technique, a windowing of a cyclic extended sequence technique or a resampling-based interpolation technique to extend the input sequence. The conversion matrix is substantially a sparse matrix.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: September 6, 2011
    Assignee: Agere Systems Inc.
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Patent number: 8001452
    Abstract: Methods and apparatus are provided for soft decision decoding using reliability values based on a log base two function. A signal is processed to determine one or more reliability values for a soft decision decoder by computing one or more log-likelihood ratio (LLR) values using a log base two function. The soft decision decoder may employ, for example, a belief propagation algorithm. The soft decision decoder can decode, for example, Low-Density Parity Check codes or turbo codes.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: August 16, 2011
    Assignee: Agere Systems Inc.
    Inventor: Kameran Azadet
  • Patent number: 7913154
    Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: March 22, 2011
    Assignee: Agere Systems Inc.
    Inventors: Kameran Azadet, Erich Franz Haratsch
  • Publication number: 20110051867
    Abstract: Methods and apparatus are provided for wireless channel estimation using interpolation elimination in the Eigen domain. Channel components at known OFDM symbol locations are interpolated to other OFDM symbol locations. Methods and apparatus are provided for interpolating in the Eigen domain between reference signals (i.e., training signals) to estimate the equalizer coefficients with a reduced complexity. In particular, one aspect of the present invention performs the required interpolation before a required matrix inversion in the Eigen domain.
    Type: Application
    Filed: August 25, 2009
    Publication date: March 3, 2011
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Joe H. Othmer, Ramon Sanchez
  • Patent number: 7868801
    Abstract: Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: January 11, 2011
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Patent number: 7868798
    Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: January 11, 2011
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Publication number: 20100304687
    Abstract: Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Ramon Sanchez
  • Patent number: 7834788
    Abstract: Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 16, 2010
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Patent number: 7808329
    Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: October 5, 2010
    Assignee: Agere Systems Inc.
    Inventors: Kameran Azadet, Fuji Yang
  • Publication number: 20100245137
    Abstract: Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Publication number: 20100245138
    Abstract: Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Publication number: 20100245136
    Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Inventors: Kameran Azadet, Samer Hijazi, Joseph H. Othmer
  • Publication number: 20100198894
    Abstract: A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Publication number: 20100198893
    Abstract: A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Publication number: 20100197264
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 5, 2010
    Applicant: Agere Systems Inc.
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez
  • Publication number: 20100198895
    Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams