Abstract: A method and apparatus are disclosed for reducing cross-talk in an unbalanced channel with a reduced number of redundancies. A cross-talk canceller is disclosed that uses a multi-dimensional finite impulse response (FIR) filter to process a received signal. Redundancies are reduced or even removed entirely by processing the signals received on each twisted pair in a vector form, using multi-dimensional finite impulse response filters. The signals received by a transceiver on each twisted pair are represented in a vector form so that the signals received on each twisted pair, and the cross-talk effect that each signal has on one another, can be performed collectively. A multi-dimensional cross-talk canceller processes a vector representation of the corresponding signals transmitted by the transceiver on each twisted pair.

Abstract: Multi-dimensional finite impulse response filters are disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (or matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

Abstract: A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N≦T.

Abstract: A duobinary optical communication system is disclosed that employs pulse amplitude modulation (PAM) techniques to provide further improvements in spectral efficiency. A disclosed PAM duobinary optical transmitter converts a plurality of input bits to an N level signal using PAM techniques; adds a current N level signal to a previous N level signal to produce a 2N−1 level signal; and converts the 2N−1 level signal to an optical signal for transmission to a receiver. A disclosed PAM duobinary optical receiver detects a power level of the received optical signal (encoded using pulse amplitude modulation and duobinary encoding techniques to encode a plurality of bits) and maps the detected power level to a plurality of bits to return the transmitted information.

Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

Abstract: A method and apparatus are disclosed for canceling cross-talk in a frequency-division multiplexed communication system. The disclosed frequency-division multiplexed communication system employs multiple carriers having overlapping channels and provides an improved cross-talk cancellation mechanism to address the resulting interference. Bandwidth compression is achieved using n level amplitude modulation in each frequency band. An FDM receiver is also disclosed that decomposes the received broadband signal into each of its respective frequency bands and returns the signal to baseband in the analog domain. Analog requirements are relaxed by removing cross-talk from adjacent RF channels, from image bands, and minimizing the performance degradation caused by In-phase and Quadrature-phase (I/Q) phase and gain mismatches in modulators and demodulators. The disclosed transmitter or receiver (or both) can be fabricated on a single integrated circuit.

Abstract: An amplitude modulated optical communication system and method are disclosed that achieve bandwidth compression by making use of an n level amplitude modulation scheme in one or more frequency bands. A soft decision decoder is disclosed that provides at least two soft slicing levels between each signal level in the multiple level transmission scheme to define an “uncertainty” region therebetween. The soft slicing levels are used to evaluate the reliability of a given bit assignment. In addition to assigning a digital value based on the received signal level, one or more soft bits are assigned indicating a “reliability” measure of the output code.

Abstract: An amplitude modulated optical communication system and method are disclosed that achieve bandwidth compression by making use of an n level amplitude modulation scheme in one or more frequency bands. The optical signal generated by a light source is monitored and a calibration scheme compensates for the non-linear effects of the light source. When the optical signal is monitored by a photo-detector at a remote receiver, the present invention compensates for the non-linear effects of the channel as well. A calibration circuit adjusts the current (or voltage) that is applied to the light source for a given signal level in the multiple level transmission scheme to thereby compensate for the non-linear effects.

Abstract: An A/D converter in which a thermometer code representing an increase in analog input voltage values is asynchronously derived using a chain of buffers, the thermometer code being translated using a binary code into a ramp voltage by a D/A converter and frozen when the ramp voltage equals the amplitude of a selected analog voltage being digitized.

Abstract: A method and apparatus are disclosed for converting a signal between the analog and digital domains using frequency interleaving. The disclosed frequency interleaving techniques can be similarly applied to convert analog signals to the digital domain or vice-versa. An analog-to-digital converter decomposes the input broadband signal into N frequency bands that are separately sampled (quantized) before a Fourier transform is applied to convert the signal into the digital domain. Each of the frequency bands can be sampled in the corresponding narrow passband using narrow-band converters, such as passband Sigma-Delta converters, or can be returned to baseband prior to sampling. The various analog samples are then converted to the digital domain using an inverse Fourier transform, or another combining technique. Both sampling and analog-to-digital conversion can be performed at a speed that is N times slower than the input frequency.

Abstract: A mixed-mode crosstalk canceller is disclosed that performs crosstalk cancellation in the continuous time domain. The disclosed mixed-mode crosstalk canceller processes the pulse amplitude modulated (PAM) digital signal to be transmitted as well as the received signal to compensate for the crosstalk between the transmit and receive signals. The output of the crosstalk canceller is subtracted from the received signal in the continuous time domain. Thus, the transmit symbol clock and the receive symbol clock can be asynchronous. The tap weights for the crosstalk cancellation are illustratively obtained using a modified version of the least mean square (LMS) algorithm for discrete time signals. The modified least mean square (LMS) algorithm is applied for continuous time signals that are derived from different clocks.

Abstract: A method and apparatus are disclosed for joint equalization and decoding of multilevel codes, such as the MLT-3 code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.

Abstract: A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE decoder for 4D-TCM includes 2D branch metric units (2D-BMU) that calculate the 2D branch metrics for the two wire pairs based on the received 2D signals.

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed. , with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract: A parallel processing decision feedback equalizer is configured to receive a plurality of symbol blocks in parallel via a plurality of corresponding input branches. It is further configured to generate a plurality of decision samples. The equalizer comprises an input buffer for storing calculated decision samples corresponding to at least one previously received symbol block and a plurality of tapped delay calculators coupled to the input buffer and located in each of the input branches which are configured to calculate the first portion of a decision feedback signal corresponding to each input branch based on the impulse response samples and the decision samples stored in said input buffer. A plurality of look-ahead-processors located in each one of the input branches and is coupled to a corresponding one of the tapped delay calculators.

Abstract: The system and method of the present invention, according to one embodiment, employs an adaptive finite impulse response filter having a second order Least Mean Square (LMS) architecture. The filter comprises a plurality of signal feedback loops coupled in parallel, each feedback loop having a correlation multiplier, a loop filter and an integrator coupled in series. Each feedback loop is configured to generate a variable tap coefficient signal. Each loop filter is configured to generate a signal corresponding to the sum of a signal received by the loop filter and the integral of the signal received by the loop filter. The output of each loop filter is provided to an integrator which in turn provides the variable tap coefficient. The filter is configured to sum the products of the tap coefficient signals with delayed versions of the input signal in a tap delay line so as to generate the output signal of the filter.

Abstract: A method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The present invention extends a parallel DFE by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency. The parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time.

Abstract: In a digital filter, data is received through an input path, and data in the filter is transported to an output through an output path. At least one delay element is disposed on the input path, and at least another delay element is disposed on the output path. The specific positions of the delay elements on the respective paths are selected to yield an optimal combination of filter parameters including the maximum computation delay, cost, and power consumption of the filter.

Abstract: A method and apparatus is provided for comparing a first input voltage to a second input voltage. In one embodiment of the invention, a first input voltage is transformed into a first current flowing through a first transistor and a second transistor. A second input voltage is transformed into a second current flowing through the first transistor while the first current continues flowing through the second transistor. A difference current is developed which represents the difference between the first current and the second current. An indicator signal is generated which indicates the larger of the first and second input voltages based on the value of the difference current.