Abstract: A scan signal driving unit capable of reducing the RC delay of scan control lines in an ultra-high resolution display, such as 8K UHD. The scan signal driving unit includes a plurality of stages configured to sequentially output scan signals, first clock lines to which first clock signals are applied, and second clock lines to which second clock signals are applied. Each of the first clock lines includes a (1-1)-th metal pattern and a (1-2)-th metal pattern disposed on the (1-1)-th metal pattern. Each of the second clock lines includes a (2-1)-th metal pattern disposed on the same layer as one of the (1-1)-th metal pattern and the (1-2)-th metal pattern.

Abstract: A display device includes a substrate, a first transistor disposed on the substrate and including a first active pattern having a first channel region, a first source region, a first drain region, and a first gate electrode, a first insulating layer disposed on the first transistor, a first electrode disposed on the first insulating layer and electrically connected to the first drain region, a second insulating layer having a first opening disposed on the first electrode, a first contact member disposed on the second insulating layer and electrically connected to the first electrode through the first opening, a third insulating layer having a second opening disposed on the first contact member, and a pixel electrode disposed on the third insulating layer and electrically connected to the first contact member through the second opening, and an emission layer disposed on the pixel electrode.

Abstract: A display device has a display area and a non-display area extending around the display area and includes: a plurality of pixels in the display area, a first voltage line in the display area; and a second voltage line in the non-display area. Each of the pixels includes an electrode pattern connected to the first voltage line, a pixel-defining film on the electrode pattern, an emission layer on the pixel-defining film, and a common electrode on the emission layer. The pixels include first-type pixels in which the common electrode and the electrode pattern are connected through an opening hole formed in the pixel-defining film and exposing part of the electrode pattern and second-type pixels in which the opening hole is not formed and the common electrode and the electrode pattern are not connected. The first-type pixels and the second-type pixels are adjacent to each other.

Abstract: According to an exemplary embodiment, an organic light emitting diode display includes: a substrate; a semiconductor layer; a first gate insulating layer disposed on the oxide semiconductor layer; a first gate layer disposed on the first gate insulating layer; a first interlayer insulating layer disposed on the first gate layer; a first data layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the first data layer; a driving voltage line and a driving low voltage line disposed on the second interlayer insulating layer and separated from each other; an upper insulating layer covering the driving voltage line and the driving low voltage line; and an anode disposed on the upper insulating layer and overlapping the driving voltage line or the driving low voltage line.

Abstract: A display device includes a first pixel including a first transistor, a second transistor, and a third transistor, a second pixel disposed adjacent to the first pixel in a first direction, and including a first transistor, a second transistor, and a third transistor, and an initialization voltage line disposed between the first pixel and the second pixel, and extending in a second direction crossing the first direction. The second transistor of the first pixel and the second transistor of the second pixel are connected to the initialization voltage line. The first, second, and third transistors of the first pixel and the first, second, and third transistors of the second pixel are symmetrical with respect to the initialization voltage line.

Abstract: An organic light emitting diode display according to exemplary embodiments includes: a data wire including a data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wire including a driving voltage line disposed in the display area and a first driving voltage line disposed in the peripheral area and extending in a first direction; and a driving low voltage wire including a cathode covering the display area and formed to the peripheral area and a first driving low voltage connection portion connected to the cathode and disposed in the peripheral area, wherein the first driving low voltage connection portion includes a first portion and a second portion having a different width than the first portion.

Abstract: A display device may include a substrate including a display area and a non-display area, pixels provided in the display area and each pixel including a pixel transistor and a light emitting element connected to the pixel transistor, a first driver provided in the non-display area and configured to provide a scan signal to the pixel, a scan line configured to transfer the scan signal to the pixel, a first fan-out line provided in the non-display area and connected to the scan line, and a first electrostatic discharge portion provided in the non-display area and located between the first fan-out line and the scan line. The first electrostatic discharge portion may include a bottom metal layer disposed on the substrate and a transistor disposed on and electrically connected to the bottom metal layer.

Abstract: A stage of a scan driver includes: a first driving controller for controlling a voltage of a first node and a voltage of a second node; a second driving controller for controlling a voltage of a first driving node, based on a sensing-on signal, a next carry signal, a first control clock signal, a second control clock signal, the voltage of the first node, and a voltage of a sampling node, and controlling a voltage of a second driving node, based on the voltage of the sampling node and the voltage of the first driving node; an output buffer for outputting a carry signal, the first scan signal, and the second scan signal; and a coupling controller. The second driving controller maintains the voltage of the first driving node as a gate-off voltage in response to the voltage of the second driving node and a third control clock signal.

Abstract: A display device including: a substrate; an active layer disposed on the substrate and including active patterns; a first conductive layer disposed on the active layer; a second conductive layer disposed on the first conductive layer and including a data line; a third conductive layer disposed on the second conductive layer; and a light-emitting element disposed on the third conductive layer, wherein the first conductive layer includes a scan line, a first voltage line, and a second voltage line, the third conductive layer includes a third voltage line connected to the first voltage line and a fourth voltage line connected to the second voltage line, the first voltage line and the second voltage line extend in a first direction, the third voltage line and the fourth voltage line extend in a second direction, and the third voltage line and the fourth voltage line are alternately arranged in the first direction.

Abstract: A display device includes a first conductive layer, a first insulation layer disposed on the first conductive layer, and active patterns disposed on the first insulation layer. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps a channel region of the active patterns and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

Abstract: A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.

Abstract: A pixel circuit includes a first switching element including a control electrode connected to a first node, an input electrode which receives a first power voltage and an output electrode connected to a third node, a second switching element including a control electrode which receives a compensation gate signal, an input electrode connected to a second node and an output electrode connected to the third node, a third switching element including a control electrode which receives a write gate signal, an input electrode connected to the first node and an output electrode connected to the second node, a storage capacitor including a first electrode which receives an initialization voltage and a second electrode connected to the first node, a program capacitor which receives a data voltage and connected to the second node, and an organic light emitting element connected to the third node and which receives a second power voltage.

Abstract: A display device includes a substrate including a plurality of light-emitting devices, a first color filter, a second color filter, and a third color filter that overlap one of the light-emitting devices, and a first color converting layer that overlaps the first color filter, a second color converting layer that overlaps the second color filter, and a transmission layer that overlaps the third color filter. A plurality of the first color filters, a plurality of the second color filters, and a plurality of the third color filters are arranged in a first direction. A gap between adjacent second color filters in a second direction overlaps the first color filter in the first direction.

Abstract: In a display device, a driving element is disposed on a rear substrate, and a passivation layer covers the driving element. A pixel electrode is disposed on the passivation layer and is connected to the driving element. An organic emission layer is disposed on the pixel electrode and is configured to emit light toward the rear substrate. A common electrode is disposed on the organic emission layer. A touch electrode is disposed between the rear substrate and the passivation layer, and it forms a capacitive component when an external touch occurs.

Abstract: A display device includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps a first channel region included in the first active pattern, the lower pattern overlaps the first active pattern, and the first active pattern does not cross an edge of the lower pattern.

Abstract: A display device includes a first conductive layer, a first insulation layer disposed on the first conductive layer, and active patterns disposed on the first insulation layer. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps a channel region of the active patterns and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

Abstract: An organic light emitting diode display including: a data wiring that includes a main data line disposed in a display area and a first data line disposed in a peripheral area; a driving voltage wiring that includes a main driving voltage line disposed in the display area and a first driving voltage line that is connected with the main driving voltage line and disposed in the peripheral area while extending in a first direction; and a driving low-voltage wiring that includes a cathode extending to the peripheral area while overlapping the display area, and a plurality of first driving low-voltage connection portions that are connected with the cathode and disposed in the peripheral area, wherein each of the plurality of first driving low-voltage connection portions comprises a wiring portion extended in the first direction and a pad portion electrically connected with the wiring portion.

Abstract: A display device having high resolution includes: a first conductive layer, an active pattern, second to fourth conductive layers, and a pixel electrode sequentially formed on a substrate, with first to fourth insulating layers separately interposed therebetween, the first conductive layer including a lower pattern, the active pattern including a source region, a channel region, and a drain region, the second conductive layer including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode, the third conductive layer including a capacitor electrode overlapping the driving gate electrode, the fourth conductive layer including an additional capacitor electrode overlapping the capacitor electrode.

Abstract: A scan signal driver including: a plurality of stages for outputting scan signals and sensing signals, wherein a kth stage among the stages is connected to a kth scan signal line and a kth sensing signal line, and wherein the kth stage includes: a first output unit configured to output a scan clock signal input to a fit scan clock terminal to the kth scan signal line as a kth scan signal and to output a sensing clock signal input to a first sensing clock terminal to the kth sensing signal line as a k sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a kth carry signal to a carry output terminal when the pull-up node has the gate-on voltage.

Abstract: A display device includes a substrate that includes a display area and a non-display area. A driver is disposed in the non-display area, and includes a driver circuit including a transistor and a driver control line transmitting a control signal to the driver circuit. A static electricity blocking line is disposed in the non-display area and circumscribes the display area. The static electricity blocking line at least partially overlaps the driver.