Abstract: A scan signal driver including: a plurality of stages for outputting scan signals and sensing signals, wherein a kth stage among the stages is connected to a kth scan signal line and a kth sensing signal line, and wherein the kth stage includes: a first output unit configured to output a scan clock signal input to a fit scan clock terminal to the kth scan signal line as a kth scan signal and to output a sensing clock signal input to a first sensing clock terminal to the kth sensing signal line as a k sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a kth carry signal to a carry output terminal when the pull-up node has the gate-on voltage.

Abstract: A display device includes a first pixel including a first transistor, a second transistor, and a third transistor, a second pixel disposed adjacent to the first pixel in a first direction, and including a first transistor, a second transistor, and a third transistor, and an initialization voltage line disposed between the first pixel and the second pixel, and extending in a second direction crossing the first direction. The second transistor of the first pixel and the second transistor of the second pixel are connected to the initialization voltage line. The first, second, and third transistors of the first pixel and the first, second, and third transistors of the second pixel are symmetrical with respect to the initialization voltage line.

Abstract: A display device includes a substrate that includes a display area for displaying an image and a non-display area surrounding the display area, a plurality of pixels that are disposed in the display area and each include an organic light emitting diode and a pixel circuit portion configured to operate the organic light emitting diode, and a scan driver that is disposed in the non-display area and includes a plurality of stages configured to output scan signals to the plurality of pixels. The plurality of stages may be arranged in n columns, a height of one stage may correspond to a height of n pixels, and n may be an integer of 2 or more.

Abstract: There are provided a gate driver and a display device including the same. The gate driver includes: a first scan driver; a first sensing driver; a first scan clock line; and a first sensing clock line. The first scan clock line includes a first scan clock main line extending in one direction, and a first scan clock connection line connected to the first scan clock main line and the first scan driver. The first sensing clock line includes a first sensing clock main line extending in one direction, and a first sensing clock connection line connected to the first sensing clock main line and the first sensing driver. The first scan clock main line is closer to each of the first scan driver and the first sensing driver than the first sensing clock main line.

Abstract: An organic light emitting diode display includes a clock wiring circuit including a first signal line and a second signal line, a resistance adjusting circuit including a first lower resistance line and a first upper resistance line connected to the first signal line and a second lower resistance line and a second upper resistance line connected to the second signal line, and a gate driving circuit connected to the resistance adjusting circuit. The second signal line is disposed closer to the gate driving circuit than the first signal line, the first lower resistance line and the second lower resistance line have higher resistivity than the first upper resistance line and the second upper resistance line, respectively, the first lower resistance line is shorter than the second lower resistance line, and the first upper resistance line is longer than the second upper resistance line.

Abstract: A display device including a substrate including a display area and an opening area therein, a data conductive layer on the substrate and including a source electrode and a voltage wiring in the opening area, a protective layer on the data conductive layer and covering the source electrode and the voltage wiring, a pixel electrode layer including a pixel electrode connected to the source electrode through a first contact hole, and an electrode pattern connected to the voltage wiring through a second contact hole, a pixel defining layer including an opening exposing the pixel electrode and a hole exposing the electrode pattern, a light emitting layer on the pixel defining layer and a common electrode on the light emitting layer, wherein the hole does not overlap the first and second contact holes.

Abstract: A scan driver includes stages configured to output a scan signal and a sensing signal, wherein an i-th (where i is an odd number) stage includes a common circuit configured to control voltages of a first node and a second node in response to a previous carry signal, a first carry control clock signal, and a second carry control clock signal, to control a voltage of a sampling node in response to a sensing on signal and a subsequent carry signal, and to control voltages of a first drive node and a second drive node based on the voltages of the first node, the second node, the sampling node, and a sensing clock signal, and a first output buffer configured to output the scan signal and the sensing signal to an i-th pixel row in response to the voltages of the first drive node and the second drive node.

Abstract: The present disclosure relates to a display device, and the display device according to an exemplary embodiment of the present inventive concept includes: a first pixel circuit portion including at least one transistor; a second pixel circuit portion including at least one transistor; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; a first data line electrically connected to the first pixel circuit portion; and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.

Abstract: A scan driver includes stages configured to output a scan signal and a sensing signal, wherein an i-th (where i is an odd number) stage includes a common circuit configured to control voltages of a first node and a second node in response to a previous carry signal, a first carry control clock signal, and a second carry control clock signal, to control a voltage of a sampling node in response to a sensing on signal and a subsequent carry signal, and to control voltages of a first drive node and a second drive node based on the voltages of the first node, the second node, the sampling node, and a sensing clock signal, and a first output buffer configured to output the scan signal and the sensing signal to an i-th pixel row in response to the voltages of the first drive node and the second drive node.

Abstract: A display device includes a substrate including a display area and a non-display area around the display area; a transistor on the substrate; an insulating layer on the transistor; a power voltage line on the insulating layer and transferring a power voltage; a data line on the insulating layer and transferring a data voltage; and an auxiliary wire between the substrate and the power voltage line in the display area. The auxiliary wire includes a portion overlapping the power voltage line and a portion overlapping the data line in a plan view and is electrically connected to the power voltage line.

Abstract: A display device may include a substrate including a display area and a non-display area, pixels provided in the display area and each pixel including a pixel transistor and a light emitting element connected to the pixel transistor, a first driver provided in the non-display area and configured to provide a scan signal to the pixel, a scan line configured to transfer the scan signal to the pixel, a first fan-out line provided in the non-display area and connected to the scan line, and a first electrostatic discharge portion provided in the non-display area and located between the first fan-out line and the scan line. The first electrostatic discharge portion may include a bottom metal layer disposed on the substrate and a transistor disposed on and electrically connected to the bottom metal layer.

Abstract: A display panel includes: a pixel region comprising a plurality of pixels; an open/short test region comprising a plurality of open/short test pads; a dummy stage configured to generate a carry signal in response to a scan start signal; and a plurality of stages configured to sequentially provide a plurality of scan signals to the plurality of pixels in response to the carry signal, wherein the plurality of stages is spaced apart by a first distance from the pixel region, and the dummy stage is spaced apart by a second distance greater than the first distance from the open/short test region.

Abstract: There are provided a gate driver and a display device including the same. The gate driver includes: a first scan driver; a first sensing driver; a first scan clock line; and a first sensing clock line. The first scan clock line includes a first scan clock main line extending in one direction, and a first scan clock connection line connected to the first scan clock main line and the first scan driver. The first sensing clock line includes a first sensing clock main line extending in one direction, and a first sensing clock connection line connected to the first sensing clock main line and the first sensing driver. The first scan clock main line is closer to each of the first scan driver and the first sensing driver than the first sensing clock main line.

Abstract: A display device includes a substrate that includes a display area and a non-display area. A driver is disposed in the non-display area, and includes a driver circuit including a transistor and a driver control line transmitting a control signal to the driver circuit. A static electricity blocking line is disposed in the non-display area and circumscribes the display area. The static electricity blocking line at least partially overlaps the driver.

Abstract: A display device includes a substrate, a metal layer disposed on the substrate, a first conductive layer including a lower pattern disposed on the metal layer, an active layer disposed on the first conductive layer, a second conductive layer disposed on the active layer and including a first gate electrode, a pixel electrode disposed on the second conductive layer, and an emission layer and a common electrode disposed on the pixel electrode.

Abstract: A display device includes a first conductive layer, a first insulation layer disposed on the first conductive layer, and active patterns disposed on the first insulation layer. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps a channel region of the active patterns and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.

Abstract: A pixel includes first, second, and third transistors, first and second capacitors, and an organic light emitting diode. The first transistor has a gate electrode connected to a first node, a first electrode that receives a first power voltage, and a second electrode connected to a second node. The second transistor has a gate electrode that receives a scan signal, a first electrode connected to the first node, and a second electrode connected to a third node. The third transistor has a gate electrode that receives a common control signal, a first electrode connected to the third node, and a second electrode connected to the second node. The organic light emitting diode has a first electrode connected to the second node and a second electrode that receives a second power voltage.

Abstract: A display device includes a substrate, a first transistor disposed on the substrate and including a first active pattern having a first channel region, a first source region, a first drain region, and a first gate electrode, a first insulating layer disposed on the first transistor, a first electrode disposed on the first insulating layer and electrically connected to the first drain region, a second insulating layer having a first opening disposed on the first electrode, a first contact member disposed on the second insulating layer and electrically connected to the first electrode through the first opening, a third insulating layer having a second opening disposed on the first contact member, and a pixel electrode disposed on the third insulating layer and electrically connected to the first contact member through the second opening, and an emission layer disposed on the pixel electrode.

Abstract: A display device includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps a first channel region included in the first active pattern, the lower pattern overlaps the first active pattern, and the first active pattern does not cross an edge of the lower pattern.

Abstract: A display device having high resolution includes: a first conductive layer, an active pattern, second to fourth conductive layers, and a pixel electrode sequentially formed on a substrate, with first to fourth insulating layers separately interposed therebetween, the first conductive layer including a lower pattern, the active pattern including a source region, a channel region, and a drain region, the second conductive layer including a gate electrode overlapping the channel region and a driving gate electrode connected to the gate electrode, the third conductive layer including a capacitor electrode overlapping the driving gate electrode, the fourth conductive layer including an additional capacitor electrode overlapping the capacitor electrode.