Abstract: A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.

Abstract: A semiconductor device includes a horizontal arrangement of switching elements including nano sheets, horizontal conductive lines, vertical conductive lines, and data storage elements. The horizontal conductive lines surround the nano sheets. Each of the vertical conductive lines is coupled to a corresponding one of first edges of the nano sheets in the horizontal arrangement. Each of the data storage elements is coupled to a corresponding one of second edges of the nano sheets in the horizontal arrangement. The semiconductor device further includes supporters, a first spacer, and a second spacer. The supporters are disposed between the vertical conductive lines. The first spacer has a single layer structure disposed between the data storage elements and the horizontal conductive lines and surrounding the nano sheets. The second spacer has a multi-layer structure disposed between the vertical conductive lines and the horizontal conductive lines and surrounding the nano sheets.

Abstract: A semiconductor device includes a first substrate; a memory cell array, a second substrate, and a back-side power distribution network. The memory cell array includes memory cells that are vertically stacked over the first substrate. The second substrate including a front side facing the memory cell array and a back side at a higher level than the front side. The second substrate further includes a plurality of control circuits for controlling the memory cells. The back-side power distribution network includes a power interconnection that penetrates the second substrate and supplies power to the control circuits from the back side of the second substrate. The memory cell array is electrically connected to the plurality of control circuits of the second substrate by a bonding structure.

Abstract: A semiconductor device includes switches including nano sheets and horizontal conductive lines surrounding the nano sheets. The semiconductor device includes first contact nodes formed on first edges of the nano sheets, and vertical conductive lines including pyramid portions surrounding the first contact nodes. Each of the vertical conductive lines is coupled to a corresponding one of the nano sheets. The semiconductor device includes data storage devices each coupled to a corresponding one of second edges of the nano sheets. The semiconductor device includes a supporter surrounding the vertical conductive lines.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.

Abstract: A semiconductor device includes a common conductive line extending in a first direction; a memory cell array including a plurality of horizontal layers stacked in the first direction while sharing the common conductive line; and a selector structure operatively coupled to the common conductive line, wherein the selector structure includes, a plurality of select transistors stacked in the first direction; and a selector commonly coupled to the select transistors.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.

Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.

Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming a first opening that passes through the stack, forming a blocking layer in the first opening, forming a data storage layer in the blocking layer, forming a slit passing through the stack, forming second openings by selectively removing the second material layers through the slit, selectively forming a protective layer on exposed surfaces of the first material layers, etching the blocking layer through the second 10 openings, oxidizing the protective layer, and forming insulating layers in the second openings.

Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.

Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming a first opening that passes through the stack, forming a blocking layer in the first opening, forming a data storage layer in the blocking layer, forming a slit passing through the stack, forming second openings by selectively removing the second material layers through the slit, selectively forming a protective layer on exposed surfaces of the first material layers, etching the blocking layer through the second openings, oxidizing the protective layer, and forming insulating layers in the second openings.

Abstract: A semiconductor device including highly integrated memory cells and a method for fabricating the same. The semiconductor device may include: a vertical conductive line; a horizontal layer horizontally oriented from the vertical conductive line and including a first horizontal portion and a second horizontal portion thinner than the first horizontal portion; a horizontal conductive line crossing the first horizontal portion of the horizontal layer; and a data storage element including a first electrode including a merged double cylinder coupled to the second horizontal portion of the horizontal layer.

Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor layer pattern over a lower structure; forming a gate dielectric layer to cover surfaces of the semiconductor layer pattern; forming a conductive layer over the gate dielectric layer to surround the semiconductor layer pattern, the conductive layer including a first edge portion and a second edge portion that are facing each other; and forming a pair of horizontal conductive lines vertically overlapping the semiconductor pattern by horizontally recessing the first edge portion and the second edge portion of the conductive layer.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.

Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device may include a gate stack structure having a stepped structure, which includes a plurality of interlayer insulating layers and a plurality of conductive layers, a tubular insulating layer penetrating the stepped structure of the gate stack structure, and a conductive gate contact connected to an end portion of one of the plurality of conductive layers, the conductive gate contact extending to a central region of the tubular insulating layer.

Abstract: A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.

Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.