Patents by Inventor Kang Sik Choi

Kang Sik Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250024680
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20240431109
    Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.
    Type: Application
    Filed: September 6, 2024
    Publication date: December 26, 2024
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 12137563
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: November 5, 2024
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20240357807
    Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming a first opening that passes through the stack, forming a blocking layer in the first opening, forming a data storage layer in the blocking layer, forming a slit passing through the stack, forming second openings by selectively removing the second material layers through the slit, selectively forming a protective layer on exposed surfaces of the first material layers, etching the blocking layer through the second 10 openings, oxidizing the protective layer, and forming insulating layers in the second openings.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 12120879
    Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: October 15, 2024
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 12063777
    Abstract: A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming a first opening that passes through the stack, forming a blocking layer in the first opening, forming a data storage layer in the blocking layer, forming a slit passing through the stack, forming second openings by selectively removing the second material layers through the slit, selectively forming a protective layer on exposed surfaces of the first material layers, etching the blocking layer through the second openings, oxidizing the protective layer, and forming insulating layers in the second openings.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: August 13, 2024
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20240224500
    Abstract: A semiconductor device including highly integrated memory cells and a method for fabricating the same. The semiconductor device may include: a vertical conductive line; a horizontal layer horizontally oriented from the vertical conductive line and including a first horizontal portion and a second horizontal portion thinner than the first horizontal portion; a horizontal conductive line crossing the first horizontal portion of the horizontal layer; and a data storage element including a first electrode including a merged double cylinder coupled to the second horizontal portion of the horizontal layer.
    Type: Application
    Filed: July 12, 2023
    Publication date: July 4, 2024
    Inventors: Hye Won YOON, Seung Hwan KIM, Kang Sik CHOI
  • Publication number: 20240215216
    Abstract: A method for fabricating a semiconductor device includes: forming a semiconductor layer pattern over a lower structure; forming a gate dielectric layer to cover surfaces of the semiconductor layer pattern; forming a conductive layer over the gate dielectric layer to surround the semiconductor layer pattern, the conductive layer including a first edge portion and a second edge portion that are facing each other; and forming a pair of horizontal conductive lines vertically overlapping the semiconductor pattern by horizontally recessing the first edge portion and the second edge portion of the conductive layer.
    Type: Application
    Filed: May 26, 2023
    Publication date: June 27, 2024
    Inventors: Seung Hwan KIM, Kang Sik CHOI
  • Publication number: 20240081066
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20240032272
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.
    Type: Application
    Filed: October 2, 2023
    Publication date: January 25, 2024
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 11856777
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20230413553
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device may include a gate stack structure having a stepped structure, which includes a plurality of interlayer insulating layers and a plurality of conductive layers, a tubular insulating layer penetrating the stepped structure of the gate stack structure, and a conductive gate contact connected to an end portion of one of the plurality of conductive layers, the conductive gate contact extending to a central region of the tubular insulating layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: December 21, 2023
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20230397415
    Abstract: A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 7, 2023
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 11837639
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11812602
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a first stacked body including a first stacked insulating layer and a first stacked conductive layer that are alternately stacked; a capacitor plug passing through the first stacked body; and a capacitor multi-layered layer configured to enclose the capacitor plug. The capacitor plug may include metal.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: November 7, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20230354603
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a sub-block insulating layer interposed between a first select gate structure and a second select gate structure, a plurality of conductive patterns stacked over first and second select gate structures to be spaced apart from each other, and a channel structure penetrating one of the first and second select gate structures and the plurality of conductive patterns, the channel structure including an inflection point located at a level between the sub-block insulating layer and the plurality of conductive patterns.
    Type: Application
    Filed: October 13, 2022
    Publication date: November 2, 2023
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20230309305
    Abstract: The present disclosure provides a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a channel layer including a plurality of channel pillars that pass through a gate stack and a channel connection portion that extends from each of the plurality of channel pillars to overlap with the gate stack, a memory layer including a vertical portion between the plurality of channel pillars and the gate stack and a horizontal portion that extends from the vertical portion between the gate stack and the channel connection portion, and a doped semiconductor layer contacting the channel connection portion and overlapping with the channel connection portion.
    Type: Application
    Filed: September 23, 2022
    Publication date: September 28, 2023
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20230292507
    Abstract: There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a stack structure including a contact region with a stepped structure, a stepped groove having a sidewall formed of the stepped structure of the stack structure, a barrier insulating layer extending along a surface of the stepped structure, a filling insulating layer formed on the barrier insulating layer inside the stepped groove, and a conductive gate contact penetrating the stepped structure of the stack structure while penetrating the filling insulating layer and the barrier insulating layer.
    Type: Application
    Filed: September 9, 2022
    Publication date: September 14, 2023
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20230282603
    Abstract: A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.
    Type: Application
    Filed: June 30, 2022
    Publication date: September 7, 2023
    Inventors: Sung Lae OH, Sang Hyun SUNG, Hyun Soo SHIN, Kang Sik CHOI
  • Patent number: 11751384
    Abstract: A semiconductor memory device includes a first stack including lower conductive patterns separated from each other and stacked on a substrate to form a lower stepped structure, a support pillar passing through the first stack and including an insulating layer, a second stack including upper conductive patterns separated from each other and stacked on the first stack, the upper conductive patterns including an upper stepped structure that does not overlap with the lower stepped structure and the support pillar, a channel structure passing through the second stack and the first stack, and a memory layer surrounding a sidewall of the channel structure.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi