Abstract: The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.

Abstract: A semiconductor device includes a well structure having a well dopant, a gate stack structure including first, second, and third stack structures stacked over the well structure, and a channel pattern penetrating the gate stack structure. A sidewall of the gate stack structure is formed with a groove in its sidewall between the first stack structure and the third stack structure such that the first stack structure and the third stack structure protrude farther than the second stack structure in a direction perpendicular to a stacking direction. The channel pattern extends along a surface of a horizontal space between the well structure and the gate stack structure. The semiconductor device further includes a memory pattern extending along an outer wall of the channel pattern, a spacer insulating pattern formed on the sidewall of the gate stack structure, and a doped semiconductor pattern formed on the spacer insulating pattern.

Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.

Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.

Abstract: A semiconductor device and manufacturing method includes a well structure, a gate stack structure spaced apart from the well structure, the gate stack structure being disposed over the well structure, and a source contact structure facing a sidewall of the gate stack structure. The semiconductor device further includes a channel pattern having pillar parts penetrating the gate stack structure, a first connecting part extending along a bottom surface of the gate stack structure from the pillar parts, and a second connecting part extending from the first connecting part to contact a first surface of the source contact structure facing the well structure.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pillar extending in a first direction and a first conductive pattern surrounding the channel pillar. The semiconductor device also has second conductive patterns surrounding the channel pillar above the first conductive pattern, wherein the second conductive patterns are stacked in the first direction and spaced apart from each other. The semiconductor device further has an etch stop pattern disposed above the first conductive pattern and below the second conductive patterns.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.

Abstract: There is provided a semiconductor device. The semiconductor device includes a source layer, a well pickup layer formed on the source layer, a body structure formed on the well pickup layer and including a well region contacting the well pickup layer and first junctions formed on side walls of the body structure, channel pillars contacting the body structure and protruding from the body structure, and contact layers formed on the side walls of the body structure and electrically connecting the body structure and the well pickup layer.

Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.

Abstract: The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.