Patents by Inventor Kang Sik Choi

Kang Sik Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134832
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.
    Type: Application
    Filed: June 22, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 10978476
    Abstract: The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10961450
    Abstract: The present invention relates to a metal fluoride red phosphor and an application of the phosphor as a light emitting element, the metal fluoride red phosphor having a tetragonal crystal structure of a novel composition, and emitting light in the red color wavelength by being excited by ultraviolet rays or a blue excitation source, thereby being usefully applicable to a light emitting element such as a light emitting diode, a laser diode, a surface emitting laser diode, an inorganic electroluminescence element, and an organic electroluminescence element.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 30, 2021
    Assignee: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Chang Hae Kim, Bo Geuk Bang, Kang Sik Choi, June Kyu Park, Min Seuk Kim, Kee Sun Sohn
  • Patent number: 10950700
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10930657
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20210043742
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Application
    Filed: October 12, 2020
    Publication date: February 11, 2021
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20200411550
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 10861866
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pillar extending in a first direction and a first conductive pattern surrounding the channel pillar. The semiconductor device also has second conductive patterns surrounding the channel pillar above the first conductive pattern, wherein the second conductive patterns are stacked in the first direction and spaced apart from each other. The semiconductor device further has an etch stop pattern disposed above the first conductive pattern and below the second conductive patterns.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10840344
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20200343261
    Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.
    Type: Application
    Filed: July 10, 2020
    Publication date: October 29, 2020
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 10811428
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20200312879
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Application
    Filed: June 16, 2020
    Publication date: October 1, 2020
    Applicant: SK hynix Inc.
    Inventors: Sang Yong LEE, Sang Min KIM, Jung Ryul AHN, Sang Hyun OH, Seung Bum CHA, Kang Sik CHOI
  • Patent number: 10770475
    Abstract: A semiconductor device includes a well structure having a well dopant, a gate stack structure including first, second, and third stack structures stacked over the well structure, and a channel pattern penetrating the gate stack structure. A sidewall of the gate stack structure is formed with a groove in its sidewall between the first stack structure and the third stack structure such that the first stack structure and the third stack structure protrude farther than the second stack structure in a direction perpendicular to a stacking direction. The channel pattern extends along a surface of a horizontal space between the well structure and the gate stack structure. The semiconductor device further includes a memory pattern extending along an outer wall of the channel pattern, a spacer insulating pattern formed on the sidewall of the gate stack structure, and a doped semiconductor pattern formed on the spacer insulating pattern.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: September 8, 2020
    Assignee: Sk hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10727247
    Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Yong Lee, Sang Min Kim, Jung Ryul Ahn, Sang Hyun Oh, Seung Bum Cha, Kang Sik Choi
  • Publication number: 20200227437
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Publication number: 20200212187
    Abstract: A semiconductor device and manufacturing method includes a well structure, a gate stack structure spaced apart from the well structure, the gate stack structure being disposed over the well structure, and a source contact structure facing a sidewall of the gate stack structure. The semiconductor device further includes a channel pattern having pillar parts penetrating the gate stack structure, a first connecting part extending along a bottom surface of the gate stack structure from the pillar parts, and a second connecting part extending from the first connecting part to contact a first surface of the source contact structure facing the well structure.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Applicant: SK hynix Inc.
    Inventor: Kang Sik CHOI
  • Patent number: 10644022
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10644014
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include a source select line. The semiconductor device may include word lines. The semiconductor device may include a channel layer. The semiconductor device may include a source structure. The source structure may be disposed under the source select line. The source structure may be in contact with the channel layer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10629691
    Abstract: A semiconductor device and manufacturing method includes a well structure, a gate stack structure spaced apart from the well structure, the gate stack structure being disposed over the well structure, and a source contact structure facing a sidewall of the gate stack structure. The semiconductor device further includes a channel pattern having pillar parts penetrating the gate stack structure, a first connecting part extending along a bottom surface of the gate stack structure from the pillar parts, and a second connecting part extending from the first connecting part to contact a first surface of the source contact structure facing the well structure.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Publication number: 20200020719
    Abstract: The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventor: Kang Sik CHOI