Abstract: The present invention is directed to flux compositions and uses thereof. One composition comprises an activator, a medium-viscosity solvent being a polymer, and a high-viscosity solvent being a copolymer containing first monomers and second monomers. Another composition comprises an activator, and a high-viscosity solvent comprising a copolymer containing first monomers and second monomers. Another composition comprises an activator of 6-12 percent by weight of glutaric acid, pimelic acid, tartaric acid, or mixtures thereof, and a medium-viscosity solvent of 88-94 percent by weight comprising a polymer with hydroxyl end groups. Another composition comprises an activator in a liquid state comprising poly(ethylene glycol)-diacid, and a medium-viscosity solvent comprising a polymer with hydroxyl end groups. A soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

Abstract: The present invention relates to a compressor in which a rotary member is suspended on a stationary member and rotated to compress the refrigerant. In the stationary member, top and bottom ends of a stationary shaft are fixed to improve the structural stability and assembly property. Bearing covers are provided on a contact portion of the stationary member and the rotary member such that the rotary member can be rotated when suspended on the stationary member. This stabilizes the operation. In the rotary member, a vane is integrally formed with a roller and mounted on a vane mounting hole of a cylinder-type rotor. This reduces the vibration and prevents refrigerant leakage to improve the compression effect. Although the rotary member is provided on an outer circumferential surface of the stationary member, it is possible to perform the suction and discharge of the refrigerant in the axial direction. This can lower the product height.

Abstract: The present invention relates to a compressor in which a rotary member suspended on a stationary member is rotated to compress the refrigerant. The rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member, which achieves the structural stability and allows the components to be easily centered and assembled. A refrigerant suction passage and a refrigerant discharge passage are improved such that the refrigerant can be sucked and discharged without a valve.

Abstract: The present invention relates to a compressor in which a rotary member suspended on a stationary member is rotated to compress the refrigerant. The rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member to thereby achieve the structural stability, improve the operation reliability and reduce the vibration. The components can be easily centered and assembled with an excellent assembly property. In addition, a mounting structure of an elastically-supported vane is improved to ensure the lubrication performance and the operation reliability. Moreover, a mounting structure of a roller-incorporated vane is improved to reduce vibration and prevent refrigerant leakage, which leads to high compression efficiency.

Abstract: The present invention relates to a compressor in which a rotary member suspended on a stationary member is rotated to compress the refrigerant. As the rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member, components can be easily centered and assembled with the structural stability. In addition, the oil stored in a hermetic container is supplied to a lubrication passage provided between the rotary member and the stationary member. This reduces a friction loss between the components and achieves the operation reliability. Moreover, the oil is easily introduced into a vane mounting hole in which a vane is linearly reciprocated. This reduces the friction and abrasion of the vane and improves the operation reliability.

Abstract: Provided is an air conditioning system comprised of a plurality of indoor units connected to each other in parallel, each having an expansion valve, and an outdoor unit including a plurality of compressors, in which at least one of the compressors provided to the outdoor unit is a capacity modulation compressor including an electromotive driving unit for driving a plurality of compression units capable of selectively compressing a working fluid, and the electromotive driving unit for the capacity modulation compressor has a stator with a coil wound around thereon and a rotor rotating inside the stator, the rotor being an LSPRM including a rotor core, flux barriers, permanent magnets and conductive bars.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.

Abstract: A method of forming a wafer level stack structure, including forming a first wafer including a first device chip, wherein the first device chip includes a plurality of input/output (I/O) pads, forming a second wafer including a second device chip, wherein each second device chip contains a second plurality of I/O pads, the second device chip is approximately equal in size to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including a first device chip having a first plurality of input/output (I/O) pads and a second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected.

Abstract: The invention relates to a composition of matter comprising a soldering flux, wherein the flux consists essentially of a combination of a fluxing agent and a solvent, and wherein the fluxing agent comprises a keto acid such as levulinic acid or acetylbutyric acid. The flux may also comprises an ester acid, or comprises a mixture of the keto acid with the ester acid. The solvent comprises a mixture of a tacky solvent with a non-tacky solvent. The invention also relates to a process comprising soldering at least two surfaces together, each of which comprises a metal area to which solder can adhere by employing the following steps in any order: applying solder to at least one of the metal areas, aligning the metal areas so that they are superimposed over one another, heating at least one of the areas to a temperature that comprises at least the melting temperature of the solder. The last step comprises joining the superimposed areas to one another.

Abstract: Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.