Patents by Inventor Kang Yeh

Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954329
    Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 9, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20240004554
    Abstract: A partial erasing management method, a memory storage device, and a memory control circuit unit are provided. The method includes: performing a first partial erasing operation on a first physical region among multiple physical regions in a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data into the first physical region; and in response to at least one of the first partial erasing operation and the first programming operation, updating first status information related to the first physical region.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 4, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11816355
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes receiving first data from a host system; sending a first write command sequence instructing continuous writing of the first data to a plurality of first chip enabled (CE) regions in response to the memory storage device being in a first state; receiving second data from the host system; and sending a second write command sequence instructing continuous writing of the second data to at least one second CE region in response to the memory storage device being in a second state. A data amount of the first data is equal to a data amount of the second data. A total number of the first CE regions is greater than a total number of the at least one second CE region.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 14, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20230297233
    Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.
    Type: Application
    Filed: April 15, 2022
    Publication date: September 21, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11687444
    Abstract: A data managing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: receiving a write command for writing a plurality of first data into a rewritable non-volatile memory module; when the plurality of first data are continuous data, writing the plurality of first data respectively into a plurality of first physical erasing units by using a single-page programming mode, and recording first management information corresponding to the plurality of first physical erasing units; and when the plurality of first data are not the continuous data, writing the plurality of first data respectively into a plurality of second physical erasing units by using the single-page programming mode.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: June 27, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11455243
    Abstract: A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units; reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units; identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation; and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 27, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20220283740
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes receiving first data from a host system; sending a first write command sequence instructing continuous writing of the first data to a plurality of first chip enabled (CE) regions in response to the memory storage device being in a first state; receiving second data from the host system; and sending a second write command sequence instructing continuous writing of the second data to at least one second CE region in response to the memory storage device being in a second state. A data amount of the first data is equal to a data amount of the second data. A total number of the first CE regions is greater than a total number of the at least one second CE region.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 8, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11409596
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: August 9, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20220245024
    Abstract: An encoding control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first data units by a plurality of first host to device (H2D) access operations; generating at least one first parity unit according to the first data units; transmitting the first parity unit to the host system by at least one first device to host (D2H) access operation; reading a plurality of second data units by a plurality of second H2D access operations; generating at least one second parity unit according to the first parity unit and the second data units without reading the first parity unit from the host system; transmitting the second parity unit to the host system by at least one second D2H access operation; and storing the first data units and the second data units to a first physical unit.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 4, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20220147443
    Abstract: A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units; reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units; identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation; and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.
    Type: Application
    Filed: December 7, 2020
    Publication date: May 12, 2022
    Inventor: Chih-Kang Yeh
  • Patent number: 11190217
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: obtaining a data; encoding a plurality of sub-data in the data to obtain a plurality of first error checking and correction codes respectively corresponding to the plurality of sub-data; writing the plurality of sub-data and the plurality of first error checking and correction codes into a first physical programming unit; encoding the plurality of sub-data to obtain a second error checking and correction code; and writing the second error checking and correction code into a second physical programming unit.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: November 30, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Chih-Kang Yeh
  • Patent number: 11144210
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11126366
    Abstract: A data erasing method, a memory control circuit unit and a memory storage device are provided. The method includes selecting a first physical erasing unit group from a plurality of physical erasing unit groups, and performing an erase operation to the first physical erasing unit group, wherein the first physical erasing unit group includes a plurality of first physical erasing units, and the number of at least one second physical erasing unit used to perform the erasing operation at the same time point of the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 21, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11048433
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The memory control method includes: performing a first write operation to write first data to a first physical unit in a first physical group through a first channel; performing a limited data collection operation to collect second data, wherein the limited data collection operation limits that the second data does not include data to be collected from the first physical group after the first write operation is completed; and performing a second write operation during a period of performing the first write operation, so as to write the second data to a second physical unit in the second physical group through a second channel. In addition, the limited data collection operation and the second write operation are configured to release at least one spare physical unit.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: June 29, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 11010290
    Abstract: Exemplary embodiments of the disclosure provide a memory management method for a rewritable non-volatile memory module including the following steps. A host write operation is performed to receive a write command from a host system and store a first data corresponding to the write command to a first physical unit. A first updating data corresponding to the host write operation is recorded. A data merge operation is performed to read a second data from a second physical unit and store the second data to a third physical unit. A second updating data corresponding to the data merge operation is recorded. A management information is read from the rewritable non-volatile memory module to a buffer memory and updated in the buffer memory according to the first updating data and the second updating data.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 18, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10997067
    Abstract: A data storing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a first data; determining whether a wear degree value of a rewritable non-volatile memory module is less than a threshold; if the wear degree value of the rewritable non-volatile memory module is less than the threshold, storing the first data into the rewritable non-volatile memory module by using a first mode; and if the wear degree value of the rewritable non-volatile memory module is not less than the threshold, storing the first data into the rewritable non-volatile memory module by using a second mode. A reliability of the first data stored by using the first mode is higher than a reliability of the first data stored by using the second mode.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: May 4, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10977116
    Abstract: A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 13, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20210073117
    Abstract: A data managing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: receiving a write command for writing a plurality of first data into a rewritable non-volatile memory module; when the plurality of first data are continuous data, writing the plurality of first data respectively into a plurality of first physical erasing units by using a single-page programming mode, and recording first management information corresponding to the plurality of first physical erasing units; and when the plurality of first data are not the continuous data, writing the plurality of first data respectively into a plurality of second physical erasing units by using the single-page programming mode.
    Type: Application
    Filed: October 14, 2019
    Publication date: March 11, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20210004173
    Abstract: A data erasing method, a memory control circuit unit and a memory storage device are provided. The method includes selecting a first physical erasing unit group from a plurality of physical erasing unit groups, and performing an erase operation to the first physical erasing unit group, wherein the first physical erasing unit group includes a plurality of first physical erasing units, and the number of at least one second physical erasing unit used to perform the erasing operation at the same time point of the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.
    Type: Application
    Filed: August 22, 2019
    Publication date: January 7, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20200401322
    Abstract: A valid data merging method, a memory control circuit unit, and a memory storage device are provided. The method includes: obtaining a first system parameter corresponding to a first region and a second system parameter corresponding to a second region; determining whether the first system parameter is greater than the second system parameter; selecting a third physical erasing unit from the second region preferentially and performing a valid data merging operation by using the third physical erasing unit when the first system parameter is greater than the second system parameter; and selecting a fourth physical erasing unit from the first region preferentially and performing the valid data merging operation by using the fourth physical erasing unit when the first system parameter is not greater than the second system parameter.
    Type: Application
    Filed: July 31, 2019
    Publication date: December 24, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh