Patents by Inventor Kang Yeh

Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10423524
    Abstract: A memory storage device, a memory control circuit unit and a data storage method for a rewritable non-volatile memory module are disclosed. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit in a first management unit and not storing the first data to the rewritable nonvolatile memory module if a data content of the first data is identical to a data content of second data stored in the first physical unit. The method also includes storing logical-to-physical bit map information to a second physical unit in the first management unit, wherein the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit. Identifiers or symbols of data content may be compared to determine if first and second data are identical.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 24, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20190196903
    Abstract: A data protecting method, a memory control circuit unit and a memory storage apparatus are provided. The method includes generating a first temporary parity code group based on first data written into a first super physical unit; generating a second temporary parity code group by performing a logic operation on second data written into a second super physical unit and the first temporary parity code group; and generating an updated parity code group by performing the logic operation on the second temporary parity code group and the first data when data of the first super physical unit all become invalid data.
    Type: Application
    Filed: March 1, 2018
    Publication date: June 27, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10310941
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 4, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Chih-Kang Yeh, Yu-Cheng Hsu, Szu-Wei Chen
  • Patent number: 10283196
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 7, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Po-Yung Chang
  • Publication number: 20190114226
    Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming units; writing a second data into a second physical programming units; encoding by using the first data without using the second data to generate a first encoded data; encoding by using the second data and a first sub-data of the first data to generate a second encoded data; and writing the first encoded data and the second encoded data into a third physical programming unit and a fourth physical programming unit.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 18, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Chih-Kang Yeh, Yu-Cheng Hsu, Szu-Wei Chen
  • Publication number: 20190065101
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a first write command from a host system; determining whether to write a first data corresponding to the first write command by using a first mode or write the first data by using a second mode according to an available buffer memory state; writing the first data into a first physical erasing unit among a plurality of physical erasing units by using the first mode when the first data is determined to be written by using the first mode; and writing the first data into a second physical erasing unit among the physical erasing units by using the second mode when the first data is determined to be written by using the second mode.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 28, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20190034329
    Abstract: An exemplary embodiment of the disclosure provides a data storage method for a rewritable non-volatile memory module. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit of a first management unit and not storing the first data to the rewritable non-volatile memory module if a data content of the first data is identical to a data content of second data, and the second data is stored in the first physical unit; and storing logical-to-physical bit map information to a second physical unit in the first management unit, and the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 31, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10191840
    Abstract: A mapping table updating method for a rewritable non-volatile memory module is provided. The method includes: allocating a mapping table storage area for storing a physical address-logical address mapping table in a buffer memory. The method also includes: determining whether a remaining storage space of the mapping table storage area is less than a threshold. If the remaining storage space is less than the threshold, mapping information of the physical address-logical address mapping table stored in the mapping table storage area is updated into at least one logical address-physical address mapping table, and the mapping information of the physical address-logical address mapping table stored in the mapping table storage area is cleared. The method also includes: storing updated mapping information corresponding to a programmed active physical erasing unit into the mapping table storage area.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: January 29, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chang-Han Hsieh
  • Publication number: 20190026227
    Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided.
    Type: Application
    Filed: September 17, 2017
    Publication date: January 24, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10169224
    Abstract: A data protecting method, a memory storage apparatus and a memory control circuit unit are provided. The method includes: determining whether a first procedure being executed or about to be executed by the memory storage device is a first type procedure; and if the first procedure being executed or about to be executed by the memory storage device is the first type procedure, temporarily stopping receiving a first data corresponding to a first write command before the first procedure is finished.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: January 1, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10162747
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes: compressing data to generate first data; determining whether a data length of the first data meets a predetermined condition. The method also includes: if the data length of the first data meets the predetermined condition, writing the first data into a first physical erasing unit among a plurality of physical erasing units; if the data length of the first data does not meet the predetermined condition, generating dummy data according to a predetermined rule, padding the first data with the dummy data to generate second data and writing the second data into the first physical erasing unit. A data length of the second data meets the predetermined condition.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: December 25, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20180353991
    Abstract: Disclosed are a graphene material and a manufacturing method thereof. A high molecule powder material is uniformly mixed with a blend of carbon black and graphene to form a material mixture. An electrostatic spraying operation is conducted by using an electrostatic spray gun to spray the material mixture of the high molecule powder material, carbon black, and graphene to a surface of a substrate so as to form a graphene coating layer such that the substrate supports the graphene coating layer. The high molecule powder material is at least 10 grains and the blended carbon black and graphene takes weight percentage of 1-10%. Carbon black is distributed in graphene so that mutual contact between carbon black and graphene and material properties of carbon black that show high conductivity makes electrical charges contained in the graphene material easy to move.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: Wei-Song Hung, Yun-Kang Yeh, Chien-Chieh Hu, Kueir-Rarn Lee, Juin-Yih Lai
  • Patent number: 10152426
    Abstract: A mapping table loading method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first command; loading a first sub-logical address-physical address mapping table corresponding to the first command if an operating mode of a non-volatile rewritable memory module is a first operating mode; and loading a first logical address-physical address mapping table corresponding to the first command if the operating mode of the non-volatile rewritable memory module is a second operating mode, wherein the first logical address-physical address mapping table includes the first sub-logical address-physical address mapping table.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: December 11, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20180335942
    Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes: receiving a read command instructing reading data from a plurality of logical addresses; selecting a plurality of logical addresses meeting a preset condition among the logical addresses, wherein the selected logical addresses include a first logical address mapping to a first physical programming unit and a second logical address mapping to a second physical programming unit, wherein the preset condition includes that the first physical programming unit belongs to a first plane, the second physical programming unit belongs to a second plane, the first plane and the second plane are different and belong to a same die, and a first address index value of the first physical programming unit is different from a second address index value of the second physical programming unit; and reading data belonging to the selected logical addresses in parallel.
    Type: Application
    Filed: July 13, 2017
    Publication date: November 22, 2018
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10102121
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: configuring a plurality of first type super physical units and at least one second type super physical unit, where one first type super physical unit includes at least two available physical erasing units which may be programmed simultaneously, and one second type super physical unit includes at least two available physical erasing units which may not be programmed simultaneously. The method also includes: configuring the first type super physical unit as to be programmed based on a first programming mode or a second programming mode, and configuring the second type super physical unit as to be programmed only based on the first programming mode.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 16, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10062418
    Abstract: A data programming method and a memory storage device are provided. The method includes: programming a plurality of first type physical units in a rewritable non-volatile memory module to store first data; encoding the first data to generate encoded data; receiving second data; and programming at least one of a plurality of second type physical units in the rewritable non-volatile memory module corresponding to the first type physical units to store at least a part of the second data after the first data is encoded. Therefore, the correcting ability for correcting errors in pair physical units in multi-channel programming procedure may be improved.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 28, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10013187
    Abstract: A mapping table accessing method for a rewritable non-volatile memory module is provided. The method includes: storing a mapping record corresponding to a first physical erasing unit into the first physical erasing unit, wherein the mapping record of the first physical erasing unit is a mapping relation of physical programming units in the first physical erasing unit. The method further includes: storing a mapping record corresponding to a second physical erasing unit into the second physical erasing unit, wherein the mapping record of the second physical erasing unit is a mapping relation of physical programming units in the second physical erasing unit. A size of the mapping record of the first physical erasing unit is different from a size of the mapping record of the second physical erasing unit.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 3, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10009045
    Abstract: A decoding method, a memory controlling circuit unit and a memory storage device are provided. The decoding method includes: performing a first type decoding operation for a first frame including a first codeword to obtain a second codeword. The method also includes: recording error estimate information corresponding to the first frame according to an execution result of the first type decoding operation. The method further includes: updating the first codeword in the first frame to the second codeword if the error estimate information matches a first condition; and performing a second type decoding operation for a block code including the first frame.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 26, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 10001928
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: June 19, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9983799
    Abstract: A trim command processing method for a memory storage apparatus having a rewritable non-volatile memory module having a plurality of physical programming units is provided. The method includes receiving a command from a host system; starting a trim operation to perform an operation corresponding to a trim command according to a record related to the trim command in a trim table if an operation corresponding the command is performed on the rewritable non-volatile memory module with a first mode; and not starting aforesaid trim operation if the operation corresponding the command is performed on the rewritable non-volatile memory module with a second mode.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: May 29, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh