Abstract: A semiconductor structure includes a substrate, a first device disposed on the substrate and a second device disposed on the substrate. The first device includes a first plurality of nanosheets comprising a p-type material. The second device includes a second plurality of nanosheets comprising an n-type material. A dielectric isolation pillar is disposed between the first device and the second device.

Abstract: An apparatus includes a substrate that has an upper face; a first electrode that is attached to the upper face of the substrate; a second electrode that is attached to the upper face of the substrate at a distance from the first electrode; and a bridge of phase-change-memory material that is attached to and lies along the upper face of the substrate between and electrically connecting the first and second electrodes. At least a portion of the bridge is thermally switchable between a low resistance solid phase and a high resistance solid phase. In some embodiments, the apparatus also includes access devices that are disposed between the electrodes and the substrate, with the bridge being electrically connected between the access devices. At least a portion of the bridge is thermally switchable between a low resistance solid phase and a high resistance solid phase.

Abstract: A microelectronic structure including a first nano device that includes a plurality of first transistors and a second nano device that includes a plurality of second transistors. The first nano device and the second nano device are parallel to each other. A doubled diffusion break that extends across the first nano device and the second nano device. A back-end-of-the-line (BEOL) layer located on a frontside of the first nano device and the second nano device. A backside interconnect located on a backside of the first nano device and the second nano device and the BEOL layer is connected to the backside interconnect through the double diffusion break.

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

Abstract: Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Abstract: A method of wafer verification for split manufacturing is provided. The method includes capturing images of one or more different wafer features during manufacturing using a fiducial marker. The method further includes comparing the images from one stage to a next stage for at least two stages of manufacturing to verify a wafer identification based on a matching of the one of more different wafer features from the one stage to the next stage.

Abstract: Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET1 below a top VTFET1, and a bottom VTFET2 below a top VTFET2, and a method of forming a stacked VTFET device are also provided.

Abstract: A method of forming a fin field effect device is provided. The method includes forming one or more vertical fins on a substrate and a fin template on each of the vertical fins. The method further includes forming a gate structure on at least one of the vertical fins, and a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer. The method further includes forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one vertical fin. The method further includes forming a sacrificial spacer on opposite sides of the fin templates and the top spacer layer, and removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the vertical fins.

Abstract: A memory cell structure includes a substrate having formed thereon a first electrode and second electrodes physically spaced apart. A phase change material (PCM) cell is formed on the substrate and forms a bridge extending between the first and second electrodes, the phase change material including a first end electrically contacting the first electrode and a second end contacting the second electrode. The phase change material cell includes a thinned surface portion where a surface topography of the phase change material cell is decreased relative to a surface topography of the phase change material cell surface at the first and second ends. The PCM thickness is intentionally gradually tapered to localize the formation of the phase change region. During PCM programming, corresponding to the weight update in machine learning, the phase change of the PCM occurs at the thinnest surface portion and gradually propagates towards the electrodes.

Abstract: A deep-via structure includes at least one via-interfacing layer. The deep-via structure also includes a via. The via is embedded within the at least one via-interfacing layer. The via includes a conductive material. The deep-via structure also includes a stress-relief void that is formed within the conductive material of the via.

Abstract: A semiconductor structure comprises a source/drain region, a spacer layer on a first side of the source/drain region, a contact on a top surface of the source/drain region, and a via connected to a portion of the contact at a second side of the source/drain region, the second side of the source/drain region being opposite the first side of the source/drain region.

Abstract: A semiconductor device includes a field effect transistor (FET) with at least one Gate-All-Around (GAA) channel. A first conductive ferromagnetic Source/Drain contact is electrically connected with a first portion of the GAA channel. A second conductive ferromagnetic Source/Drain contact is electrically connected with a second portion of the GAA channel. A remanent magnetization of the first conductive ferromagnetic contact is oriented in a direction opposite to a remanent magnetization of the second conductive ferromagnetic contact.

Abstract: A semiconductor structure includes a first transistor device, a second transistor device, and a dielectric pillar structure disposed between the first transistor device and the second transistor device. The dielectric pillar structure includes a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device.

Abstract: A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.

Abstract: A semiconductor structure including a stacked transistor structure comprising a top device stacked directly above a bottom device, and a bilayer gate dielectric layer separating the top device from the bottom device.

Abstract: A high-density electrode array, a neural probe, and a method of control thereof, the high-density electrode array including a plurality of neural electrodes, a wordline, and a bitline where each neural electrode of the plurality of neural electrodes is individually controlled by the wordline and the bitline.

Abstract: A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source/drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source/drain region.

Abstract: A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Abstract: Embodiments of present invention provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a supporting structure; forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask sequentially on top of the bottom electrode; forming an inner spacer in an opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer respectively into a second dielectric layer, a phase-change element, and a first dielectric layer; forming a conductive liner surrounding the phase-change element; and forming a top electrode on top of the heating element. A structure formed thereby is also provided.

Abstract: A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth.