Abstract: Illustrative embodiments provide techniques for fabricating semiconductor structures having bottom isolation and enhanced carrier mobility for both nFET and pFET devices. For example, in one illustrative embodiment, a semiconductor structure includes a semiconductor substrate, a first dielectric layer disposed on the semiconductor substrate, a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer, a second dielectric layer disposed on the bottom source/drain region and a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer. The bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.

Abstract: A semiconductor structure is presented including a first dielectric isolation pillar disposed between a pair of p-type field effect transistors (pFETs), a second dielectric isolation pillar disposed between a pair of n-type FETs (nFETs), a first source/drain (S/D) epi region having a first contact electrically connected to a backside power delivery network (BSPDN), the first contact being disposed on one side of the first dielectric isolation pillar, and a second S/D epi region having a second contact electrically connected to back-end-of-line (BEOL) components, the second contact being disposed on the other side of the first dielectric isolation pillar.

Abstract: A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain structure of a first field effect transistor (FET) that is present in a front side of the wafer, the second source/drain structure of the first FET is connected to a front side BEOL structure by a front side source/drain contact structure. A logic device region and/or an analog device region can be located laterally adjacent to the PCM device region. A back side power distribution network can be present in the logic device region and/or an analog device region.

Abstract: Backside and frontside contact structures wrapping around source/drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source/drain regions provides source/drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source/drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.

Abstract: A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.

Abstract: Backside self-aligned contact designs using a replacement contact process with unique placeholder profile are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a frontside of the device; backside power rails on a backside of the device; a backside source/drain region contact connecting a given one of the backside power rails to a source/drain region of the field-effect transistor(s), and a dielectric placeholder(s) between the given backside power rail and another source/drain region of the field-effect transistor(s), where a first end of the dielectric placeholder(s) having a width W1 directly contacts the given backside power rail, a second end of the dielectric placeholder(s) having a width W2 directly contacts the other source/drain region, where W1>W2. The field-effect transistor(s) can include a stack of active layers with bottom dielectric isolation, and a gate-all-around configuration.

Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the first source/drain region comprises a smaller cross-section than the second source/drain region, a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain region and further in contact with a vertical surface and top surface of the second source/drain region, and a second dielectric material disposed as an interlayer dielectric material encapsulating the first and second transistors.

Abstract: Embodiments of present invention provide a ferroelectric random-access memory (FeRAM) cell. The FeRAM cell includes a vertical channel between a bottom source/drain region and a top source/drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, wherein the ferroelectric layer has two or more sections of different horizontal thicknesses between the bottom source/drain region and the top source/drain region. A method of manufacturing the FeRAM cell is also provided.

Abstract: A semiconductor structure comprises one or more transistor devices on a first side of the semiconductor structure, one or more transistor devices on a second side of the semiconductor structure, the second side being opposite the first side, and a dielectric isolation layer separating the one or more transistor devices on the first side of the semiconductor structure from the one or more transistor devices on the second side of the semiconductor structure. The one or more transistor devices on the second side of the semiconductor structure comprise channel layers on one side of the dielectric isolation layer and source/drain regions that are independent of source/drain regions of the one or more transistor devices on the first side of the semiconductor structure.

Abstract: Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizontal portion and a vertical portion on top of the horizontal portion; a selector underneath the horizontal portion of the L-shaped phase change element; a top electrode in contact with a top surface of the vertical portion of the L-shaped phase change element; and a bottom electrode in contact with the selector; and a second PCM cell. A method of manufacturing the PCM device is also provided.

Abstract: Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.

Abstract: The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Abstract: A non-volatile memory having a 3D cross-point architecture and twice the cell density is provided in which vertically stacked word lines run in plane (i.e., parallel) to the substrate and bit lines runs perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack that includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line within each vertical stack of word lines and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line-bit line combination. Some of the bit lines are located in the dielectric material stack and some of the bit lines are located in an interlayer dielectric material layer.

Abstract: A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.

Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

Abstract: A phase change memory (PCM) structure including a bottom electrode, a first dielectric spacer disposed above and in contact with the bottom electrode, the first dielectric spacer comprising a vertical seam, a PCM layer disposed above the first dielectric spacer, and a heater element disposed in the seam and in contact with the bottom electrode.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Abstract: A stacked semiconductor device comprising a lower source/drain epi located on top of a bottom dielectric layer. An isolation layer located on top of the lower source/drain epi and an upper source/drain epi located on top of the isolation layer. A lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi.