Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of sections from a top to a bottom thereof, wherein the plurality of sections has a same chemical composition and at least two different strains. For example, in one embodiment, the plurality of sections has a same chemical composition of epitaxially grown silicon (Si) and has alternating strains between a tensile strain and a compressive strain. A method of manufacturing the semiconductor structure is also provided.

Abstract: A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a substrate, at least a portion of one or more of the fins providing one or more channels for one or more fin field-effect transistors. The method also includes forming a plurality of active gate structures over the fins, forming at least one single diffusion break trench between a first one of the active gate structures and a second one of the active gate structures, and forming at least one double diffusion break trench between a third one of the active gate structures and a fourth one of the active gate structures. The double diffusion break trench has a stepped height profile in the substrate, the stepped height profile comprising a first depth with a first width and a second depth less than the first depth with a second width greater than the first width.

Abstract: A non-volatile memory structure, and methods of manufacture, which may include a first memory element and a second memory element between a first terminal and a second terminal. The first memory element and the second memory element may be in parallel with each other between the first and second terminal. This may enable the hybrid non-volatile memory structure to store values as a combination of the conductance for each memory element, thereby enabling better tuning of set and reset conductance parameters.

Abstract: A complementary metal-oxide-semiconductor field effect transistor structure (C-MOSFET) includes a substrate; a dielectric pillar that is embedded in and recessed into the substrate; a gate pillar that contacts the dielectric pillar and protrudes from the substrate; a first stack of semiconductor nanosheets that protrude from a first side of the gate pillar; and a second stack of semiconductor nanosheets that protrude from a second side of the gate pillar, opposite the first side.

Abstract: Semiconductor devices and methods of forming the same include forming a buried power rail in a substrate, having a first dielectric liner of a first thickness separating the buried power rail from the substrate. An isolation structure is formed over the buried power rail, having a second dielectric liner of a second thickness, greater than the first thickness, separating the isolation structure from the substrate. A first transistor device is formed on the substrate. The first transistor device has a first width. A second transistor device is formed above the first transistor device, and has a second width smaller than the first width. A conductive contact is formed to the buried power rail.

Abstract: A field effect device is provided. The field effect device includes a stack of nano-channels on a substrate, wherein each of the nano channels has a first height, a first width, and a first length, and a vertical nanosheet perpendicular to a major plane of the substrate on opposite sides of the stack of nano-channels, wherein each of the vertical nanosheets has a second height, a second width, and a second length, wherein the second height of the vertical nanosheets is greater than the first width of the nano-channels. The field effect device further includes a gate dielectric layer wrapped around at least a portion of each of the nano-channels and the vertical nanosheets, and a conductive gate fill on the gate dielectric layer.

Abstract: A gate-all-around device is provided. The gate-all-around device includes a source/drain on a substrate, an isolation liner wrapped around the source/drain, where the isolation liner separates the source/drain from the substrate, and a one or more nanosheet channel sections electrically connected to the source/drain.

Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin.

Abstract: Embodiments of the present invention are directed to a semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. A dielectric pillar is positioned adjacent to the nanosheet stack and on a shallow trench isolation region of the substrate. The nanosheet stack is recessed to expose a surface of the shallow trench isolation region and a source or drain (S/D) region is formed on the exposed surface of the shallow trench isolation region. A contact trench is formed that exposes a surface of the S/D region and a surface of the dielectric pillar.

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: Embodiments of the present disclosure provide a semiconductor structure including a first sidewall spacer positioned between a first gate terminal and a first source/drain terminal of a first active device. The first sidewall spacer includes a first L-shaped spacer and a first outer spacer. The L-shaped spacer having a base portion and a vertical portion vertically extended, parallel to the first outer spacer, to a top portion of a first inter dielectric layer (IDL). A RDB dielectric, having a reduced width less than a width of the first gate terminal. The RDB dielectric vertically extends from the top portion of the IDL into the substrate. The RDB dielectric is separated from the first source/drain terminal by first RDB spacer, the first RDB spacer includes a first upper spacer. The first RDB spacer has a reduced width less that the first sidewall spacer width.

Abstract: A method, phase change memory array, and system for controlling heater height variation in phase change memories using a multi-step selective stop method. The method may include depositing a first dielectric layer. The method may also include depositing a second dielectric layer proximately connected to the first dielectric layer, where the second dielectric layer is different than the first dielectric layer. The method may also include depositing a heating material. The method may also include performing a first selective stop to remove excess heating material above the second dielectric layer. The method may also include performing a second selective stop to remove the second dielectric layer.

Abstract: A phase change bridge memory cell includes: a first interlevel dielectric layer; a first electrode and a second electrode disposed in the first interlevel dielectric layer and separated by a portion of the first interlevel dielectric layer; an interlevel dielectric pillar on the portion of the first interlevel dielectric layer; a first phase change material on the interlevel dielectric pillar; and a second phase change material including two areas on opposite sides of the interlevel dielectric pillar and electrically connected by the first phase change material, wherein the second phase change material is connected to the first electrode and the second electrode.

Abstract: Embodiments herein describe semiconductor devices with single diffusion breaks that are narrower than the gates of transistors in those devices. That is, rather than forming the diffusion breaks using a dummy gate (which would result in the diffusion breaks having the same width as the gates of the transistors) the embodiments herein use different means to establish the width of the diffusion break. As a result, the diffusion break can be narrower than traditional diffusion breaks formed using dummy gates, thereby saving area in the semiconductor device.