Abstract: A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding circuit having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.

Abstract: A semiconductor structure includes: a high-speed circuit module including a clock signal with a frequency greater than a first threshold; a first conductive metal layer including power conductive wires extending along a first direction and arranged at intervals, and the power conductive wires being electrically connected with the high-speed circuit module; and a redistribution layer located above the first conductive metal layer and including power pads and electrical wires connected with the power pads, in which the power pads are located at one side of the high-speed circuit module, a projection of the power pads does not overlap with that of the high-speed circuit module, the electrical wires include a first electrical wire region where the electrical wires are repeatedly bent, the first electrical wire region at least partially covers the high-speed circuit module, and the electrical wires are used for electrically connecting the power conductive wires and power pads.

Abstract: A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.

Abstract: A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.

Abstract: Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.

Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.

Abstract: An address signal transmission circuit includes a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, where the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal; and a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, where the selection circuit inverts the second address signal to obtain the address inverted signal.

Abstract: A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.

Abstract: A data writing method and a memory, in which the data writing method is used for writing data to a memory array of the memory. The data writing method includes that: old data is read from a target column of the memory array; the old data is updated according to data to be written which carries target data bits information to generate new data; and the new data is written into the target column, in which the memory includes a plurality of data columns, the data is required to be written into the target column, and the target column includes a part of the data columns.

Abstract: Provided is a memory system, which includes: a memory, configured to, during a read or write operation, write or read multiple data, the multiple data are divided into M bytes, each having N data; and an encoding module, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes.

Abstract: This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

Abstract: Embodiments relate to a semiconductor memory and a method for writing data. The semiconductor memory includes: at least one storage array, the storage array including a plurality of data storage units and a plurality of check bit storage units; a check module, configured to receive written data and generate check data according to the written data; and a data transmission module, respectively connected to the check module and the storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units. A first transmission time duration of the check data is shorter than a second transmission time duration of the written data.

Abstract: A voltage conversion circuit is provided. The circuit includes a first input module and a second input module. The first input module is connected to a first voltage and has a first input terminal for receiving an input signal and outputting a conversion signal, a high level of the input signal is a second voltage which is less than the first voltage; The second input module is connected to the first input module and has a second input terminal and an output terminal, the second input terminal is configured to receive a sampling signal, and the second input module is configured to sample the conversion signal according to the sampling signal and output an output signal via the output terminal.

Abstract: Embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data writing method thereof. The storage system is configured to: enter a write data copy mode in response to a write-copy enable signal; if at least two groups of data in multiple groups of data exported from multiple data ports are a same in the write data copy mode, define the at least two groups of data as a category; generate an identification signal that is used to indicate a data copy; transmit one group of data in the category to an interface of a memory array; and disconnect a transmission path between a data port corresponding to another group of data in the category and another interface of the memory array, wherein the memory array, in response to the write-copy enable signal and the identification signal.

Abstract: The embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data reading method thereof. The storage system is configured to: enter a read data copy mode in response to a read-copy enable signal; if at least two groups of data in multiple groups of data exported from a memory array are a same in the read data copy mode, define the at least two groups of data as a category; export an identification signal that is used to indicate a data copy; transmit one group of data in the category to a corresponding data port; and disconnect a transmission path that is used to transmit another group of data in the category to a corresponding data port.

Abstract: The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.

Abstract: A data path interface circuit includes: a writing path module, connected to an internal port and an external port and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and internal port respectively, and configured to obtain the stored data from the external port or internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or reading path module; and a delay control module, connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.

Abstract: A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.

Abstract: An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y?Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.