Abstract: An error correction system includes M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y?Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals.

Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.

Abstract: A data error correction circuit includes: a data error correction circuit, configured to receive first data and a first check code corresponding to the first data, perform error correction on the first data according to the first check code to generate second data, and output the second data; and a check code generation circuit, configured to receive the first data and the first check code, generate a second check code according to the first data and the first check code, and output the second check code.

Abstract: A data transmission circuit and a data transmission method applied to the data transmission circuit are provided. The data transmission circuit includes: a data strobe module, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, where each group of data buses include an odd data line and an even data line; and an error correction module, where each group of the data buses are provided with the error correction module, the error correction module is provided on the odd data line or the even data line, and the error correction module is configured to perform error correction on data written through the low-bit data port or the high-bit data port.

Abstract: The data transmission circuit includes: at least two data transmission structures. Each data transmission structure includes a memory transmission terminal, a bus transmission terminal, and an interactive transmission terminal. Data inputted from the memory transmission terminal is outputted through the bus transmission terminal or the interactive transmission terminal. Data inputted from the bus transmission terminal is outputted through the memory transmission terminal or the interactive transmission terminal. Data inputted from the interactive transmission terminal is outputted through the bus transmission terminal or the memory transmission terminal. A control module receives an input control signal and an adjustment control signal that are provided by the memory; the control module is configured to output the input control signal in a delayed manner based on the adjustment control signal, so as to generate an output control signal corresponding to the input control signal.

Abstract: A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding module having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding module, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

Abstract: The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

Abstract: A semiconductor memory includes storage arrays, at least one verification module and gating circuits. Each verification module corresponds to multiple storage arrays. The verification module is configured to verify whether an error occurs in data information of the corresponding storage arrays. Each verification module is connected to a group of global data buses. The gating circuits are respectively connected to the storage arrays and the global data buses, and the gating circuits are configured to control on and off of a data transmission path connecting the global data buses to the storage arrays.

Abstract: A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.

Abstract: Provided are a data transmission circuit and a memory. The data transmission circuit includes: a normal reading module, which is connected to a normal storage array and configured to read and output data from the normal storage array; a redundant reading module, which is connected to a redundant storage array, and configured to read and output data from the redundant storage array; and an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform error detection operation on the read data.

Abstract: Embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data writing method thereof. The storage system is configured to: enter a write data copy mode in response to a write-copy enable signal; if at least two groups of data in multiple groups of data exported from multiple data ports are a same in the write data copy mode, define the at least two groups of data as a category; generate an identification signal that is used to indicate a data copy; transmit one group of data in the category to an interface of a memory array; and disconnect a transmission path between a data port corresponding to another group of data in the category and another interface of the memory array, wherein the memory array, in response to the write-copy enable signal and the identification signal.

Abstract: The embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data reading method thereof. The storage system is configured to: enter a read data copy mode in response to a read-copy enable signal; if at least two groups of data in multiple groups of data exported from a memory array are a same in the read data copy mode, define the at least two groups of data as a category; export an identification signal that is used to indicate a data copy; transmit one group of data in the category to a corresponding data port; and disconnect a transmission path that is used to transmit another group of data in the category to a corresponding data port.

Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.

Abstract: A pulse signal generation circuit includes a clock frequency division component, a time delay component and a selection component. The clock frequency division component is configured to perform frequency division on a clock signal to generate a clock frequency division signal; the time delay component is configured to generate a time delay signal based on the clock frequency division signal; and the selection component is configured to receive the clock frequency division signal and the time delay signal at the same time, and select the clock frequency division signal and the time delay signal according to a preset condition to generate a pulse signal.

Abstract: A voltage conversion circuit and a memory are provided. The voltage conversion circuit includes a driving circuit and a receiving circuit. The driving circuit is powered by a first voltage, and outputs a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage. The receiving circuit is powered by the first voltage, receives the first signal at a first input end, and receives a sampling signal at a second input end. The receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage.

Abstract: An error correction system is disclosed. The error correction system is applied to a storage system. The error correction system generates X first operation codes, Y second operation codes and a third operation code based on the storage system. The error correction system includes an error state determining circuit and M decoding circuits. The error state determining circuit is configured to identify a current error state. When a plurality of pieces of data have a 1-bit error, the M decoding circuits are configured to execute decoding processing on the X first operation codes and the Y second operation codes, to obtain whether there is erroneous data in the bytes corresponding to the decoding circuits and locate a bit to which the erroneous data belongs.

Abstract: A DRAM memory includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction. Each memory block has a number of memory cells arranged in rows and columns. Dividing each memory bank into three memory blocks in the column direction shortens the length of the memory bank in the row direction, as each memory bank has a certain capacity, so a large drive is no longer required. In addition, the distance from the control circuit and the data transmission circuit to the corresponding memory cell in the memory array in each memory bank will be shorter too, reducing parasitic resistance and parasitic capacitance generated from the data transmission circuit. As a result, the data transmission rate and data transmission accuracy are improved. The overall power consumption is reduced.

Abstract: Provided is a memory system, which includes: a memory, configured to, during a read or write operation, write or read multiple data, the multiple data are divided into M bytes, each having N data; and an encoding module, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes.