Abstract: A slew rate controlling system for output data is provided which is capable of improving an output data window even when change in a potential difference between a first power supply (VDD) to be used for outputting and a second power supply (VDDQ) to be used internally occurs. The slew rate controlling system is achieved by using a VDD-VDDQ potential difference detecting circuit to detect a decrease in a potential difference between the first power supply (VDD) and the second power supply (VDDQ) and to produce a first signal with specified timing and to detect an increase in a potential difference between the first power supply (VDD) and the second power supply (VDDQ) and to produce a second signal and by using a slew rate controlling circuit to exert control, when the first signal is significant, to enlarge a transition speed in a fall of output data and to exert control, when the second signal is significant, to enlarge the transition speed in a rise of output data and to produce output data.

Abstract: A parallel data outputting circuit equipped with a data inversion function, comprises P number of data comparator means, P number of majority decision circuits, P number of inversion flag generating means and P number of data inversion circuits, these being activated in parallel in one cycle. In generating an inversion flag indicating whether or not the parallel data are to be inverted and output in the inverted state, inversion flags are calculated from outputs of the inversion flag generating means and the inversion flag generating means of a cycle directly previous to a current cycle.

Abstract: A 64Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

Abstract: In a semiconductor memory device, a memory cell array has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit receives the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and receives the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit receives the even read data from the second even data bus and the odd read data from the second odd data bus, and outputs one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.

Abstract: A majority circuit for reduce a size thereof is provided. The majority circuit is composed of a D/A converter converting a plurality of binary signals to an analogue signal, a majority determining circuit responsive to said analogue signal to achieve a majority operation on said plurality of binary signals to produce a result signal representative of a result of said majority operation.

Abstract: In a semiconductor memory device, a memory cell array has an even bank activated based on even numbered addresses and an odd bank activated based on odd numbered addresses. Even read data is outputted from the even bank in response to a first control signal, and odd read data is outputted from the odd bank in response to the first read control signal. A relaying unit receives the even read data on the first even data bus to output the even read data to the second even data bus in response to a second read control signal, and receives the odd read data on the first odd data bus to output the odd read data to the second odd data bus in response to the second read control signal. An I/O circuit receives the even read data from the second even data bus and the odd read data from the second odd data bus, and outputs one of the even read data and the odd read data to the common data bus and then outputs the other to the common data bus, in response to a third read control signal.

Abstract: A 64 Mb DRAM which comprises memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W selected, the greater the number of bits that can be output.

Abstract: A 64 Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

Abstract: A semiconductor integrated circuit device is provided having a low-amplitude input/output interface for inputting or outputting an input/output signal synchronously with a clock signal and transferring the input/output signal with an amplitude corresponding to a power supply voltage to or from an external command unit. A first differential circuit to be practically continuously operated is used as an input circuit for receiving a clock signal supplied from an external clock unit. In addition, a second differential circuit is provided which is intermittently operated in accordance with the clock signal to sample an input signal in accordance with an internal clock signal generated by the first differential circuit while the second differential circuit is operated and holds the sampled signal while the second differential circuit is not operated. This second differential circuit is used as an input circuit for receiving a low-amplitude input signal inputted synchronously with the clock signal.

Abstract: In a synchronous DRAM, internal clock signals in synchronism with clock signals fed from an external unit are generated by a PLL circuit or a DLL circuit to eliminate signal delays. In order to provide a dynamic RAM that is capable of stably operating with clock signals over a wide range of frequencies; a change-over circuit is provided which changes the range of variable frequencies of the PLL circuit or changes the variable delay time of the DLL circuit based upon mode-setting information fed from an external unit.

Abstract: A semiconductor memory incorporating an operation circuit for carrying out logical operations on data and arithmetic operations on address signals. The memory is arranged functionally so that the data representing the result of each of such operations is written to a memory array while also being output through an external terminal in the same memory cycle.

Abstract: The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.

Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively.

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

Abstract: A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

Abstract: A half precharge type dynamic RAM has a pair of data lines to which a plurality of dynamic memory cells are coupled. The paired data lines are set in advance before a read operation at a reference potential which is equal to one half of the supply voltage. One of the paired data lines is switched to have a higher or lower level than the reference potential by the memory cell selected. The potential difference applied between the paired data lines is amplified by the operation of a sense amplifier. Here, an address selecting MOSFET in the memory cell has a gate capacitance which will undesirably couple a word line and the data lines. As a result, one of the data lines has its level changed in an undesired manner. The noise inparted between the paired data lines by such coupling noise components can be substantially neglected by adopting a dummy MOSFET which operates to impart coupling noise components corresponding to the noise components caused by the address selecting MOSFET gate capacitance.

Abstract: A semiconductor integrated circuit device which constitutes a dynamic RAM has an automatic refresh circuit that contains a refresh timer circuit. The refresh timer circuit has a program element such as a fuse element. The program element is programmed depending upon the data holding characteristics of the dynamic memory cells. Therefore, the refresh period is changed depending upon the characteristics of the dynamic memory cells. According to this construction, the refresh period changes and, as a result, any undesired refresh operation is prevented from being executed, making it possible to reduce the amount of electric power consumed by the circuit device.