Abstract: A semiconductor integrated circuit device which constitutes a dynamic RAM has an automatic refresh circuit that contains a refresh timer circuit. The refresh timer circuit has a program element such as a fuse element. The program element is programmed depending upon the data holding characteristics of the dynamic memory cells. Therefore, the refresh period is changed depending upon the characteristics of the dynamic memory cells. According to this construction, the refresh period changes and, as a result, any undesired refresh operation is prevented from being executed, making it possible to reduce the amount of electric power consumed by the circuit device.

Abstract: The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit can select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.

Abstract: A semiconductor integrated circuit device which constitutes a dynamic RAM has an automatic refresh circuit that contains a refresh timer circuit. The refresh timer circuit has a program element such as a fuse element. The program element is programmed depending upon the data holding characteristics of the dynamic memory cells. Therefore, the refresh period is changed depending upon the characteristics of the dynamic memory cells. According to this construction, the refresh period changes and, as a result, any undesired refresh operation is prevented from being executed, making it possible to reduce the amount of electric power consumed by the circuit device.

Abstract: The semiconductor memory device includes at least two memory arrays, a first selection circuit which selects a memory cell from either one of the memory arrays in accordance with address signals, preferably two spare memory arrays and a second selection circuit which selects a memory cell from either one of the spare memory arrays. If a defective memory cell or cells are contained in one of the two memory arrays, the second selection circuit an select a spare memory cell or cells from any of the two spare memory arrays in place of the defective memory cell or cells. Thus, the spare memory arrays can be used effectively. Two sets of main amplifiers are also disposed and only one of them, which receives the data from the memory cell selected from the memory arrays or spare memory arrays, is operated. Thus, lower power consumption can be realized.

Abstract: A pseudo-static type RAM composed of dynamic type memory cells is operated in response to the changes in external address signals. In the RAM of this type, the word line, with which the selection terminals of the memory cells are connected, are selected only for such a remarkably short time period as responds to the abnormally short period for which the external address signals are changed by address skews. If the selection period of the word line is short, the signal level to be rewritten in the memory cells is dropped so that the stored data are substantially broken. In order to prevent this breakage of the stored data, an address buffer is controlled. The reception of the external address signals by the address buffer is prohibited during the time period after the selection of the word line is started and before the rewriting operation of the data in the memory cells is ended.