Patents by Inventor Kanwal Jit Singh

Kanwal Jit Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321282
    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Boyan BOYANOV, Kanwal Jit SINGH
  • Patent number: 10727183
    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Kanwal Jit Singh
  • Patent number: 10593627
    Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Kanwal Jit Singh, Kevin Lin, Robert Lindsey Bristol
  • Publication number: 20190393157
    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.
    Type: Application
    Filed: September 3, 2019
    Publication date: December 26, 2019
    Inventors: Boyan BOYANOV, Kanwal Jit SINGH
  • Patent number: 10457548
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Lai Lin, Chytra Pawashe, Raseong Kim, Ian A. Young, Kanwal Jit Singh, Robert L. Bristol
  • Patent number: 10446493
    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Kanwal Jit Singh
  • Patent number: 10147639
    Abstract: A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Kanwal Jit Singh, Alan M. Myers
  • Patent number: 10032643
    Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers
  • Publication number: 20180145035
    Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.
    Type: Application
    Filed: June 25, 2015
    Publication date: May 24, 2018
    Inventors: Kanwal Jit SINGH, Kevin LIN, Robert Lindsey BRISTOL
  • Publication number: 20180086627
    Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 29, 2018
    Inventors: Kevin LAI LIN, Chytra PAWASHE, Raseong KIM, Ian A. YOUNG, Kanwal Jit SINGH, Robert L. BRISTOL
  • Patent number: 9887161
    Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (?-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Christopher J. Jezewski, David J. Michalak, Kanwal Jit Singh, Alan M. Myers
  • Publication number: 20170330761
    Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
    Type: Application
    Filed: December 22, 2014
    Publication date: November 16, 2017
    Inventors: Jasmeet S. CHAWLA, Ruth A. BRAIN, Richard E. SCHENKER, Kanwal Jit SINGH, Alan M. MEYERS
  • Patent number: 9754886
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Boyan Boyanov, Kanwal Jit Singh, James Clarke, Alan Myers
  • Publication number: 20170250104
    Abstract: A method including forming a sacrificial material between metal lines of an integrated circuit structure; forming a mask on the sacrificial material; and after forming the mask, removing the sacrificial material to leave a void between the metal lines. An apparatus including an integrated circuit substrate; a first metallization level on the substrate; a second metallization; and a mask disposed between the first metallization level and the second metallization level, the mask including a dielectric material having a porosity select to allow mass transport therethrough, wherein each of the first metallization level and the second metallization level comprises a plurality of metal lines and a portion of adjacent metal lines of at least one of the first metallization level and the second metallization level are separated by voids.
    Type: Application
    Filed: December 22, 2014
    Publication date: August 31, 2017
    Inventors: Kanwal Jit SINGH, Alan M. MYERS
  • Publication number: 20170207120
    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel The channel is configured to contain the capping layer within the width of the conductive line.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Boyan Boyanov, Kanwal Jit Singh
  • Publication number: 20170148868
    Abstract: Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Applicant: INTEL CORPORATION
    Inventors: NICK LINDERT, JOSEPH M. STEIGERWALD, KANWAL JIT SINGH
  • Patent number: 9659869
    Abstract: Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Christopher J Jezewski, Alan M Meyers, Kanwal Jit Singh, Tejaswi K Indukuri, James S Clarke, Florian Gstrein
  • Patent number: 9627321
    Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Kanwal Jit Singh
  • Patent number: 9565766
    Abstract: Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Joseph M. Steigerwald, Kanwal Jit Singh
  • Patent number: 9553018
    Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Kevin Lin, Kanwal Jit Singh, Alan M. Myers, Richard E. Schenker