Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (?-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (?-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer.

Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

Abstract: Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (?-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer.

Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.