Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits.

Abstract: Fully encapsulated conductive lines are generally described. For example, a first dielectric layer is formed on a substrate. Copper wiring is disposed below a top surface of the first dielectric layer. A barrier metal layer is formed over the copper wiring, the barrier metal layer flush with the top surface of the first dielectric layer, and a second dielectric layer is formed on the barrier metal layer and the top surface of the first dielectric layer. Other embodiments are also disclosed and claimed.

Abstract: Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.

Abstract: Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H2O2), a hydroxide source, and a corrosion inhibitor. The hydrogen peroxide and hydroxide source have the capability to remove the hard mask while the corrosion inhibitor prevents the metal conductor layer from chemically reacting with the hydrogen peroxide and hydroxide source during the hard mask removal.