Abstract: A laser structure, including: a dielectric matrix formed of a first material; a laser source formed within the dielectric matrix and formed of a semiconductor material; and a plurality of side confining features formed within the dielectric matrix and extending parallel to and along a length of the laser source. The plurality of side confining features are formed of the semiconductor material.

Abstract: Structures including an edge coupler and methods of forming a structure including an edge coupler. The structure includes a waveguide core over a dielectric layer and a back-end-of-line stack over the dielectric layer and the waveguide core. The back-end-of-line stack includes a side edge and a truncated layer that is overlapped with a tapered section of the waveguide core. The truncated layer has a first end surface adjacent to the side edge and a second end surface above the tapered section of the waveguide core. The truncated layer is tapered from the first end surface to the second end surface.

Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

Abstract: Structures and methods implement an enlarged waveguide. The structure may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a semiconductor substrate. An inter-level dielectric (ILD) layer is over the SOI substrate. A first waveguide has a lower surface extending at least partially into the buried insulator layer, which allows vertical enlargement of the waveguide, without increasing the thickness of the ILD layer or increasing the length of interconnects to other devices. The enlarged waveguide may include nitride, and can be implemented with other conventional silicon and nitride waveguides.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The edge coupler includes a waveguide core, and a shaped layer is positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material. The first material may be, for example, single-crystal silicon, and the second material may be, for example, silicon nitride.

Abstract: One illustrative device disclosed herein includes a V-groove in a base semiconductor layer of a semiconductor-on-insulator (SOI) substrate, wherein the V-groove is adapted to have a fiber optics cable positioned therein, and an optical component positioned above the V-groove. The device also includes a first layer of silicon dioxide positioned above the optical component, a second layer of silicon dioxide positioned on and in contact with the first layer of silicon dioxide and a third layer of silicon dioxide positioned on and in contact with the second layer of silicon dioxide.

Abstract: Embodiments of the disclosure provide a demultiplexer for processing a multiplexed optical input. The demultiplexer may include a plurality of Mach-Zehnder Interferometric (MZI) stages for converting the multiplexed optical input into a plurality of component optical signals. Each of the plurality of component optical signals corresponds to a respective wavelength-space component of the multiplexed optical input. A plurality of bandpass filters, each having a respective wavelength passband, may receive one of the plurality of component optical signals. The plurality of bandpass filters generates a plurality of demultiplexed optical signals based on the plurality of component optical signals.

Abstract: Structures including a waveguide core and methods of fabricating a structure that includes a waveguide core. A dielectric layer including a trench with a first sidewall and a second sidewall, and a waveguide core positioned inside the trench between the first and second sidewalls of the trench. The waveguide core has a first width, and the trench has a second width between the first and second sidewalls that is greater than the first width.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a moisture seal for photonic devices and methods of manufacture. The structure includes: a first trench in at least one substrate material; a guard ring structure with an opening and which at least partially surrounds the first trench; and a second trench at a dicing edge of the substrate, the second trench being lined on sidewalls with barrier material and spacer material over the barrier material.

Abstract: Structures including a waveguide core and methods of fabricating a structure that includes a waveguide core. A dielectric layer including a trench with a first sidewall and a second sidewall, and a waveguide core positioned inside the trench between the first and second sidewalls of the trench. The waveguide core has a first width, and the trench has a second width between the first and second sidewalls that is greater than the first width.

Abstract: Structures for a filter and methods of fabricating a structure for a filter. The filter is coupled to a waveguide core. The filter includes a first plurality of grating structures positioned adjacent to a first section of the waveguide core and a second plurality of grating structures positioned adjacent to a second section of the waveguide core. The first plurality of grating structures are configured to cause laser light in a first portion of a wavelength band to be transferred between the first section of the waveguide core and the first plurality of grating structures. The second plurality of grating structures are configured to cause laser light in a second portion of a wavelength band to be transferred between the second section of the waveguide core and the second plurality of grating structures.

Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A tapered feature composed of a dielectric material is arranged over the waveguide. The tapered feature includes a sidewall that is angled relative to a longitudinal axis of the waveguide.

Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

Abstract: Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

Abstract: Device structures for a field-effect transistor and methods of forming such device structures using a device layer of a silicon-on-insulator substrate. A channel and an isolation region are formed in the device layer. The channel is located beneath a gate structure is formed on the device layer and is comprised of a semiconductor material under strain. A portion of the device layer is located between the first isolation region and the channel. The portion of the device layer is under a strain that is less than the strain in the semiconductor material of the channel.

Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.