Patents by Inventor Karl D. Hobart

Karl D. Hobart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9196703
    Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 24, 2015
    Assignees: Northrop Grumman Systems Corporation, The United States of America, as Represented by the Secretary of the Navy, The Regents of the University of California
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene I. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Rajinder S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
  • Patent number: 9196614
    Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride barrier material, a second material layer, a two-dimensional hole gas in the second layer, and wherein the gallium-polar material comprises one or more III-Nitride epitaxial material layers grown such that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making an inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the gallium-polar (0001) face is the dominant face, growing a nucleation layer, growing a gallium-polar epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 24, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 9159641
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 13, 2015
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Publication number: 20150221760
    Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the gallium-polar material comprises one or more III-Nitride epitaxial material layers grown such that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making an inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the gallium-polar (0001) face is the dominant face, growing a nucleation layer, growing a gallium-polar epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.
    Type: Application
    Filed: February 9, 2015
    Publication date: August 6, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Publication number: 20150221727
    Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride grown epitaxially on a substrate, a barrier, a two-dimensional hole gas in the barrier layer material at the heterointerface of the first material, and wherein the gallium-polar III-Nitride material comprises III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face of a substrate so that the gallium-polar (0001) face is the dominant face for growth of III-Nitride epitaxial layer growth material, growing a GaN epitaxial layer, doping, growing a barrier, etching, forming a contact, performing device isolation, defining a gate opening, defining gate metal, making a contact window, and depositing and defining a thick metal.
    Type: Application
    Filed: April 29, 2014
    Publication date: August 6, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 9029833
    Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: May 12, 2015
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart, Travis J. Anderson
  • Patent number: 9006791
    Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 14, 2015
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Publication number: 20150060947
    Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Andrew D. Koehler, Travis J. Anderson, Marko J. Tadjer, Tatyana I. Feygelson, Karl D. Hobart
  • Publication number: 20150056763
    Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Eugene A. Imhoff, Travis J. Anderson, Joshua D. Caldwell, Andrew D. Koehler, Bradford B. Pate, Marko J. Tadjer, Randijer S. Sandhu, Vincent Gambin, Gregory Lewis, Ioulia Smorchkova, Mark Goorsky, Jeff McKay
  • Publication number: 20140367824
    Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Applicant: The Govemment of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart, Travis J. Anderson
  • Patent number: 8900939
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 2, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart, Michael A. Mastro, Charles R. Eddy, Jr.
  • Publication number: 20140335666
    Abstract: Methods for forming a high-quality III-nitride passivation layer on an AlGaN/GaN HEMT. A III-nitride passivation layer is formed on the surface of an AlGaN/GaN HEMT by means of atomic layer epitaxy (ALE), either before or after deposition of a gate metal electrode on the AlGaN barrier layer. Depending on the gate metal and/or the passivation material used, the III-nitride passivation layer can be formed by ALE at temperatures between about 300° C. and about 850° C. In a specific embodiment, the III-nitride passivation layer can be an AlN layer formed by ALE at about 550° C. after deposition of a Schottky metal gate electrode. The III-nitride passivation layer can be grown so as to conformally cover the entire device, providing a hermetic seal that protects the against environmental conditions.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 13, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Andrew D. Koehler, Travis J. Anderson, Karl D. Hobart, Francis J. Kub
  • Patent number: 8872159
    Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 28, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart
  • Publication number: 20140264777
    Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Marko J. Tadjer, Tatyana I. Feygelson, Bradford B. Pate, Travis J. Anderson
  • Publication number: 20140264379
    Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.
    Type: Application
    Filed: January 31, 2014
    Publication date: September 18, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 8753468
    Abstract: A method for reducing graphene film thickness on a donor substrate and transferring graphene films from a donor substrate to a handle substrate includes applying a bonding material to the graphene on the donor substrate, releasing the bonding material from the donor substrate thereby leaving graphene on the bonding material, applying the bonding material with graphene onto the handle substrate, and releasing the bonding material from the handle substrate thereby leaving the graphene on the handle substrate. The donor substrate may comprise SiC, metal foil or other graphene growth substrate, and the handle substrate may comprise a semiconductor or insulator crystal, semiconductor device, epitaxial layer, flexible substrate, metal film, or organic device.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: June 17, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Joshua D. Caldwell, Karl D. Hobart, Travis Anderson, Francis J. Kub
  • Publication number: 20140141580
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart, Michael A. Mastro, Charles R. Eddy, Jr.
  • Patent number: 8723218
    Abstract: Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 13, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Francis J. Kub, Mario Ancona, Eugene A. Imhoff
  • Publication number: 20140110722
    Abstract: Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 24, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Karl D. Hobart
  • Patent number: 8648390
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 11, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart, Charles R. Eddy, Jr., Michael A. Mastro, Travis Anderson