Patents by Inventor Karl D. Hobart

Karl D. Hobart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130240905
    Abstract: Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway.
    Type: Application
    Filed: September 6, 2012
    Publication date: September 19, 2013
    Inventors: Karl D. Hobart, Francis J. Kub, Mario Ancona, Eugene A. Imhoff
  • Publication number: 20130161641
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Application
    Filed: February 25, 2013
    Publication date: June 27, 2013
    Inventors: Francis J. Kub, Karl D. Hobart, Charles R. Eddy, JR., Michael A. Mastro, Travis Anderson
  • Patent number: 8445383
    Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: May 21, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Tatyana I Feygelson, Marko J Tadjer, Joshua D. Caldwell, Kendrick X Liu, Francis J. Kub, Michael A Mastro, James E Butler
  • Publication number: 20130082241
    Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart
  • Patent number: 8384129
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: February 26, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart, Charles R. Eddy, Jr., Michael A Mastro, Travis Anderson
  • Patent number: 8008626
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 30, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J Kub, Bernard F Phlips, Karl D Hobart, Eric A Wulf
  • Publication number: 20110127527
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Application
    Filed: January 21, 2011
    Publication date: June 2, 2011
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Bernard F. Phlips, Karl D. Hobart, Eric A. Wulf
  • Patent number: 7915143
    Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: March 29, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Joshua D. Caldwell, Robert E Stahlbush, Karl D Hobart, Marko J Tadjer, Orest J Glembocki
  • Patent number: 7902513
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: March 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Bernard F. Phlips, Karl D. Hobart, Eric A. Wulf
  • Publication number: 20110048625
    Abstract: A method for reducing graphene film thickness on a donor substrate and transferring graphene films from a donor substrate to a handle substrate includes applying a bonding material to the graphene on the donor substrate, releasing the bonding material from the donor substrate thereby leaving graphene on the bonding material, applying the bonding material with graphene onto the handle substrate, and releasing the bonding material from the handle substrate thereby leaving the graphene on the handle substrate. The donor substrate may comprise SiC, metal foil or other graphene growth substrate, and the handle substrate may comprise a semiconductor or insulator crystal, semiconductor device, epitaxial layer, flexible substrate, metal film, or organic device.
    Type: Application
    Filed: August 12, 2010
    Publication date: March 3, 2011
    Inventors: Joshua D. Caldwell, Karl D. Hobart, Travis Anderson, Francis J. Kub
  • Publication number: 20100327322
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 30, 2010
    Inventors: Francis J. Kub, Karl D. Hobart, Charles R. Eddy, JR., Michael A. Mastro, Travis Anderson
  • Publication number: 20100213380
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Application
    Filed: March 18, 2009
    Publication date: August 26, 2010
    Applicant: The Government of the United State of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Bernard F. Phlips, Karl D. Hobart, Eric A. Wulf
  • Patent number: 7759186
    Abstract: Methods for producing a junction termination extension surrounding the edge of a cathode or anode junction in a semiconductor substrate, where the junction termination extension has a controlled arbitrary lateral doping profile and a controlled arbitrary lateral width, are provided. A photosensitive material is illuminated through a photomask having a pattern of opaque and clear spaces therein, the photomask being separated from the photosensitive material so that the light diffuses before striking the photosensitive material. After processing, the photosensitive material so exposed produces a laterally tapered implant mask. Dopants are introduced into the semiconductor material and follow a shape of the laterally tapered implant mask to create a controlled arbitrary lateral doping profile and a controlled lateral width in the junction termination extension in the semiconductor.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: July 20, 2010
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Eugene A. Imhoff, Francis J. Kub, Karl D. Hobart
  • Publication number: 20100055882
    Abstract: Methods for producing a junction termination extension surrounding the edge of a cathode or anode junction in a semiconductor substrate, where the junction termination extension has a controlled arbitrary lateral doping profile and a controlled arbitrary lateral width, are provided. A photosensitive material is illuminated through a photomask having a pattern of opaque and clear spaces therein, the photomask being separated from the photosensitive material so that the light diffuses before striking the photosensitive material. After processing, the photosensitive material so exposed produces a laterally tapered implant mask. Dopants are introduced into the semiconductor material and follow a shape of the laterally tapered implant mask to create a controlled arbitrary lateral doping profile and a controlled lateral width in the junction termination extension in the semiconductor.
    Type: Application
    Filed: July 6, 2009
    Publication date: March 4, 2010
    Applicant: The Government of the United States of America, as rpresented by the Secretary of the Navy
    Inventors: Eugene A. Imhoff, Francis J. Kub, Karl D. Hobart
  • Publication number: 20090273390
    Abstract: A method of reversing Shockley stacking fault expansion includes providing a bipolar or a unipolar SiC device exhibiting forward voltage drift caused by Shockley stacking fault nucleation and expansion. The SiC device is heated to a temperature above 150° C. A current is passed via forward bias operation through the SiC device sufficient to induce at least a partial recovery of the forward bias drift.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 5, 2009
    Inventors: JOSHUA D. CALDWELL, Robert E. Stahlbush, Karl D. Hobart, Marko J. Tadjer, Orest J. Glembocki
  • Patent number: 7535100
    Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: May 19, 2009
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Publication number: 20090090918
    Abstract: A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n? and p? SiC epilayers. I-V measurements on p+ NCD/n? SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the valence band or acceptor level of the NCD film.
    Type: Application
    Filed: September 5, 2008
    Publication date: April 9, 2009
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Marko J. Tadjer, Joshua D. Caldwell, Kendrick X. Liu, Francis J. Kub
  • Patent number: 7282753
    Abstract: The Invention Is A Method For Making Power Device On A Semiconductor Wafer, Where The Backside Of The Wafer Has Been Thinned In Selected Regions To A Thickness Of About 25 Um By Reactive Ion Etching.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 16, 2007
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 7132321
    Abstract: Semiconductor substrates suitable for making thin vertical current conducting devices are made by providing a relatively thick semiconducting substrate with at least one conductivity type having a thickness of from about 100 ?m to 700 ?m. At least one active device region is optionally first formed on a first side. Then the semiconducting substrate is thinned in at least one selected region on the other side below at least partially where the active device will be on the first side so as to have the selected region thinned to a thickness ranging from about 10 ?m to 400 ?m to form at least one deep trench.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: November 7, 2006
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6856520
    Abstract: A double-side IGBT (DIGBT) phase leg architecture that uses the DIGBT as a substitute for a free wheeling diode to achieve reduced turn-on loss and reduced reverse recovery peak current during turn-on is described and characterized. Approximately a 50% reduction in reverse recovery peak current and an 80% reduction in recovery charge are achieved. In addition, low power dissipation (?1 A current level) protection circuitry is described that can be incorporated into the DIGBT phase leg architecture to allow the flow of reverse current even if the gate driver circuit is disabled so that conventional high current free wheeling diodes are not required to provide protection.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: February 15, 2005
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: John M. Neilson, Francis J. Kub, Karl D. Hobart