Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.

Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride grown epitaxially on a substrate, a barrier, a two-dimensional hole gas in the barrier layer material at the heterointerface of the first material, and wherein the gallium-polar III-Nitride material comprises III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face of a substrate so that the gallium-polar (0001) face is the dominant face for growth of III-Nitride epitaxial layer growth material, growing a GaN epitaxial layer, doping, growing a barrier, etching, forming a contact, performing device isolation, defining a gate opening, defining gate metal, making a contact window, and depositing and defining a thick metal.

Abstract: An inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a gallium-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the gallium-polar material comprises one or more III-Nitride epitaxial material layers grown such that when GaN is epitaxially grown the top surface of the epitaxial layer is gallium-polar. A method of making an inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the gallium-polar (0001) face is the dominant face, growing a nucleation layer, growing a gallium-polar epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.

Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.

Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.

Abstract: A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN high-electron-mobility transistor (HEMT). The diamond gate electrode is formed so that it directly contacts the barrier layer. In some embodiments, the diamond gate electrode is formed from boron-doped nanocrystalline diamond (NCD), while in other embodiments, the diamond gate electrode is formed from single crystal diamond.

Abstract: A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.

Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: Methods for forming a high-quality III-nitride passivation layer on an AlGaN/GaN HEMT. A III-nitride passivation layer is formed on the surface of an AlGaN/GaN HEMT by means of atomic layer epitaxy (ALE), either before or after deposition of a gate metal electrode on the AlGaN barrier layer. Depending on the gate metal and/or the passivation material used, the III-nitride passivation layer can be formed by ALE at temperatures between about 300° C. and about 850° C. In a specific embodiment, the III-nitride passivation layer can be an AlN layer formed by ALE at about 550° C. after deposition of a Schottky metal gate electrode. The III-nitride passivation layer can be grown so as to conformally cover the entire device, providing a hermetic seal that protects the against environmental conditions.

Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.

Abstract: An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.

Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.

Abstract: A method for reducing graphene film thickness on a donor substrate and transferring graphene films from a donor substrate to a handle substrate includes applying a bonding material to the graphene on the donor substrate, releasing the bonding material from the donor substrate thereby leaving graphene on the bonding material, applying the bonding material with graphene onto the handle substrate, and releasing the bonding material from the handle substrate thereby leaving the graphene on the handle substrate. The donor substrate may comprise SiC, metal foil or other graphene growth substrate, and the handle substrate may comprise a semiconductor or insulator crystal, semiconductor device, epitaxial layer, flexible substrate, metal film, or organic device.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway.

Abstract: Semiconductor devices that include a semiconductor structure integrated with one or more diamond material layers. A first diamond material layer is formed on a bottom surface and optionally, the side surfaces of the semiconductor structure. In some embodiments, at least a portion of the semiconductor structure is embedded in the diamond. An electrical device can be formed on a top surface of the semiconductor structure. A second diamond material layer can be formed on the top surface of the semiconductor structure. The semiconductor structure can include a III-nitride material such as GaN, which can be embedded within a the first diamond material layer or encased by the first and/or second diamond material layer.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: Silicon carbide PiN diodes are presented with reduced temperature coefficient crossover points by limited p type contact area to limit hole injection in the n type drift layer in order to provide a lower current at which the diode shifts from negative temperature coefficient to a positive temperature coefficient of forward voltage for mitigating thermal runaway.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.