Patents by Inventor Karl J. Bois
Karl J. Bois has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055157Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Karl J. Bois, James David Stewart, David P. Kopp, Elene Chobanyan
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Patent number: 11810689Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.Type: GrantFiled: October 12, 2020Date of Patent: November 7, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Karl J. Bois, James David Stewart, David P. Kopp, Elene Chobanyan
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Patent number: 11658080Abstract: Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.Type: GrantFiled: October 29, 2020Date of Patent: May 23, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Karl J. Bois
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Publication number: 20220418093Abstract: One aspect provides a printed circuit board (PCB). The PCB includes a transmission line to transmit signals of a desired frequency, a first stub coupled to the transmission line at a first location, and a second stub coupled to the transmission line at a second location. The first stub is to filter out signals of a first frequency, the second stub is to filter out signals of a second frequency, and the first and second stubs are positioned such that an insertion loss of the transmitted signals of the desired frequency is substantially minimized.Type: ApplicationFiled: June 29, 2021Publication date: December 29, 2022Inventors: David P. Kopp, Karl J. Bois, Steven J. Martin
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Publication number: 20220139791Abstract: Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.Type: ApplicationFiled: October 29, 2020Publication date: May 5, 2022Inventors: Melvin K. Benedict, Karl J. Bois
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Publication number: 20220115166Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.Type: ApplicationFiled: October 12, 2020Publication date: April 14, 2022Inventors: KARL J. BOIS, JAMES DAVID STEWART, DAVID P. KOPP, ELENE CHOBANYAN
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Patent number: 11281833Abstract: Systems and assemblies are provided for exchanged signal routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. Exchanged signal routing techniques involve “exchanging” the signal routing lanes on the PCB, which reduces coupled signal amplitude and phase relationship. Exchanged signal routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. A printed circuit board (PCB) can include an array of contact pads, a plurality of signal lines that include an escape route. One or more exchange junctions disposed within the escape route can route a first signal line of a first routing channel in the escape route into a second routing channel in the escape route.Type: GrantFiled: October 29, 2020Date of Patent: March 22, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Karl J. Bois
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Patent number: 11191152Abstract: A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.Type: GrantFiled: January 18, 2019Date of Patent: November 30, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Elene Chobanyan, Karl J. Bois, Christian Olsen
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Patent number: 11042683Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.Type: GrantFiled: July 22, 2016Date of Patent: June 22, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Elene Chobanyan, Karl J. Bois
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Patent number: 10771291Abstract: An example system includes a communication channel and at least one tuning structure coupled to the communication channel. The tuning structure includes a branch of the communication channel. The tuning structure is to dissipate energy from the communication channel at least at one selected wavelength. The branch of the communication channel is a terminated portion.Type: GrantFiled: January 29, 2016Date of Patent: September 8, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin Benedict, Karl J. Bois
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Publication number: 20200236777Abstract: A printed circuit board (PCB) may include a signal layer having a functional region and a PCB signal layer testing region. The PCB signal layer testing region may include a first differential pair having a first length formed on the signal layer, a second differential pair having a second length, different than the first length, formed on the signal layer and a third differential pair having a third length, different than the first length and different than the second length, formed on the signal layer.Type: ApplicationFiled: January 18, 2019Publication date: July 23, 2020Inventors: Elene Chobanyan, Karl J. Bois, Christian Olsen
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Patent number: 10499489Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer. A void of a defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines. A resistive material of the defected ground structure along a perimeter of the void improves suppression of the EMI propagated by the strip lines, via the resistive material absorbing the EMI.Type: GrantFiled: July 14, 2017Date of Patent: December 3, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Karl J. Bois, Elene Chobanyan, Benjamin Toby
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Patent number: 10491342Abstract: An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slicer by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a number of total bits and a number of erroneous bits based on the digital output signal and calculating a two-sided bit error ratio frequentist confidence interval (FCI) size from the measured bit error ratio. The measured bit error ratio is output in response to the two-sided bit error ratio FCI being less than or equal to a two-sided bit error ratio interval target size.Type: GrantFiled: July 23, 2018Date of Patent: November 26, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Benjamin Toby, David P. Kopp, Karl J Bois
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Patent number: 10477672Abstract: An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.Type: GrantFiled: January 29, 2018Date of Patent: November 12, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Karl J. Bois
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Patent number: 10445458Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.Type: GrantFiled: September 29, 2016Date of Patent: October 15, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Elene Chobanyan, Karl J Bois, Charles Andrew Hartman
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Patent number: 10372857Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.Type: GrantFiled: April 26, 2016Date of Patent: August 6, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Benjamin Toby, Karl J. Bois
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Publication number: 20190238370Abstract: An example system includes a communication channel and at least one tuning structure coupled to the communication channel. The tuning structure includes a branch of the communication channel. The tuning structure is to dissipate energy from the communication channel at least at one selected wavelength. The branch of the communication channel is a terminated portion.Type: ApplicationFiled: January 29, 2016Publication date: August 1, 2019Inventors: Melvin Benedict, Karl J. Bois
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Publication number: 20190239338Abstract: An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.Type: ApplicationFiled: January 29, 2018Publication date: August 1, 2019Inventors: Melvin K. Benedict, Karl J. Bois
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Patent number: 10356964Abstract: Examples described herein include an electromagnetic interference shield. In some examples, the electromagnetic interference shield includes a wall comprised of a conductive material. The wall may have a first surface, a second surface, and a thickness between the first surface and the second surface. The shield may include a rounded opening in the wall that creates an air passageway through the thickness of the wall. The shield may also include a first obstruction in the opening and a second obstruction in the opening. The first obstruction may span across the opening. The second obstruction may span across the opening and intersect the first obstruction. The first obstruction and the second obstruction may be waveguide structures.Type: GrantFiled: July 21, 2016Date of Patent: July 16, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Elene Chobanyan, Karl J. Bois, Dave Mayer, Arlen L. Roesner
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Publication number: 20190021164Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer. A void of a defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines. A resistive material of the defected ground structure along a perimeter of the void improves suppression of the EMI propagated by the strip lines, via the resistive material absorbing the EMI.Type: ApplicationFiled: July 14, 2017Publication date: January 17, 2019Inventors: Karl J. Bois, Elene Chobanyan, Benjamin Toby