Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the EMI propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines to minimize the EMI that the element radiates outwards as the antenna.

Abstract: One example includes a printed circuit board (PCB) structure. The PCB structure includes a first dereferenced microstrip and a first capacitor pad contacting the first dereferenced microstrip. The PCB structure includes a second dereferenced microstrip and a second capacitor pad contacting the second dereferenced microstrip. The PCB structure also includes a capacitor including a first terminal contacting the first capacitor pad and a second terminal contacting the second capacitor pad.

Abstract: A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.

Abstract: Examples describe a system that may include an input engine and a proximity verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool, may identify a particular signal net and a particular power net the particular signal net is referenced to in the electronic circuit design. The input engine may further identify a particular signal via in the electronic circuit design corresponding to the particular signal net and power vias in the electronic circuit design corresponding to the particular power net. In such examples, the proximity verification engine may also verify that the particular signal via is within a threshold distance from at least one of the power vias and generate a proximity alert in response to a determination that none of the power vias are within the threshold distance from the particular signal via.

Abstract: A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.

Abstract: A system may include an input engine and a void avoidance engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a first net and a second net in the electronic circuit design. The void avoidance engine may perform a void avoidance verification scan to determine whether the first net, the second net, or both, are within a threshold distance from any voids in the electronic circuit design. The void avoidance engine may also generate a double violation alert responsive to a determination that the first net and the second net are both within the threshold distance from a particular void in the electronic circuit design and that the first net and the second net are located on different sides of the same plane of the electronic circuit design.

Abstract: Examples described herein include an electromagnetic interference shield. In some examples, the electromagnetic interference shield includes a wall comprised of a conductive material. The wall may have a first surface, a second surface, and a thickness between the first surface and the second surface. The shield may include a rounded opening in the wall that creates an air passageway through the thickness of the wall. The shield may also include a first obstruction in the opening and a second obstruction in the opening. The first obstruction may span across the opening. The second obstruction may span across the opening and intersect the first obstruction. The first obstruction and the second obstruction may be waveguide structures.

Abstract: A apparatus comprising a printed circuit board (“PCB”). The PCB comprises a first insulating layer and a second insulating layer. The first insulating layer is made of a first material and the second insulating layer is made of a second material. The first material has a lower dissipation factor than the second material. The first material and second material have substantially similar dielectric constants.

Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the EMI propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines to minimize the EMI that the element radiates outwards as the antenna.

Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.

Abstract: One example includes a printed circuit board (PCB) structure. The PCB structure includes a first dereferenced microstrip and a first capacitor pad contacting the first dereferenced microstrip. The PCB structure includes a second dereferenced microstrip and a second capacitor pad contacting the second dereferenced microstrip. The PCB structure also includes a capacitor including a first terminal contacting the first capacitor pad and a second terminal contacting the second capacitor pad.

Abstract: An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slices by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a bit error ratio based on the digital output signal and determining a confidence level for the measured bit error ratio, and in response to the determined confidence level equaling or exceeding a specified value, designating a current value of the measured bit-error ratio as the expected bit error ratio for the corresponding time-voltage slice and ending the test operation.

Abstract: A system can include a memory circuit having a first signal via, a first signal return via, and at least one second signal return via located closer to the control signal via than the first signal return via.

Abstract: A apparatus comprising a printed circuit board (“PCB”). The PCB comprises a first insulating layer and a second insulating layer. The first insulating layer is made of a first material and the second insulating layer is made of a second material. The first material has a lower dissipation factor than the second material. The first material and second material have substantially similar dielectric constants.

Abstract: System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.

Abstract: Methods and apparatuses for affecting the frequency behavior of connections within a printed circuit board or an integrated circuit are disclosed. Some embodiments include a printed circuit board comprising, a plurality of conductive layers each comprising at least one conductive pad, where each conductive pad on the conductive layers includes a vacancy, and an insulating material disposed about the conductive layers such that the vacancies are at least partially filled with the insulating material.

Abstract: A computer-implemented method is disclosed for adjusting impedance of a differential via pair in an electrical circuit layout. A differential via pair having an odd mode characteristic impedance needing adjustment is identified in a circuit design database. A region is established around the differential via pair in which circuit elements may be modified to adjust the odd mode characteristic impedance of the differential via pair. At least one of the circuit elements in the electrical circuit layout in the established region is adjusted until the odd mode characteristic impedance is closer to a desired odd mode characteristic impedance value.

Abstract: A computer-implemented method is disclosed for adjusting impedance. A list of differential line pairs in a circuit design database is searched through for a target differential line pair, where the target differential line pair is flagged as having an incorrect characteristic impedance. A position in a circuit layout described in said circuit design database of at least one line in the differential line pair is adjusted to correct the characteristic impedance.

Abstract: A computer-implemented method is disclosed for verifying signal via impedance. Properties of a signal via and of any other vias within a given distance of the signal via are read from a circuit design database. A target characteristic impedance value for the signal via is obtained. A characteristic impedance of the signal via is calculated based on the other vias. The signal via is flagged as having an incorrect characteristic impedance if the calculated characteristic impedance does not match the target characteristic impedance value.

Abstract: A data bus for a printed circuit board is disclosed having a plurality of lines separated by a substrate. A method is also disclosed for creating a bus with a reduced reflection of signal energy at the interface between the bus and a receiving agent connected to the bus. The lines in the bus include data lines and at least two strobe lines that are positioned adjacent each other to take advantage of the known impedance inherent to their dominant coupling. The bus includes separate data-line terminations and strobe-line terminations connected to the data lines and strobe lines, respectively. The separate terminations have values matched to impedances calculated from the separate sets of lines to more effectively reduce the reflected energy by more accurately matching the impedances on the lines.