Patents by Inventor Karl J. Bois

Karl J. Bois has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6971077
    Abstract: A computer-implemented method for adjusting impedance is disclosed. A desired impedance value for a signal line in an electrical circuit layout is read, and the signal line is identified in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance adjustment for the signal line. The impedance adjustment is performed by adjusting at least one of the circuit elements in the window to bring an impedance of the signal line nearer the desired impedance value.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 29, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy C. Nelson, Karl J. Bois
  • Patent number: 6968522
    Abstract: A computer-implemented method is disclosed for verifying differential line pair impedance. Properties for a differential line pair segment are read from a circuit design database. Properties of neighboring traces are also from the circuit design database, with the neighboring traces being within a given distance of the differential line pair segment. A modal characteristic impedance of the differential line pair segment is calculated based on the neighboring traces. The differential line pair segment is flagged as having an improper impedance value if the calculated modal characteristic impedance differs from a desired modal characteristic impedance.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 22, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy C. Nelson, Karl J. Bois
  • Patent number: 6889367
    Abstract: A computer-implemented method is disclosed for verifying impedance in a differential via pair. A target differential via pair is identified in a design database. A desired modal characteristic impedance for the target differential via pair is obtained. A two-dimensional window is established around the differential via pair in which neighboring vias will be included in a modal characteristic impedance calculation for the target differential via pair. A modal characteristic impedance for the target differential via pair is calculated based at least in part on the neighboring vias in the two-dimensional window. The target differential via pair is flagged if the calculated modal characteristic impedance does not match the desired modal characteristic impedance.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: May 3, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy C. Nelson, Karl J. Bois
  • Patent number: 6859915
    Abstract: A computer-implemented method for verifying impedance of a signal line in an electrical circuit layout includes reading a desired impedance value for a signal line and identifying the signal line in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance calculation for the signal line. The impedance of the signal line is calculated based on the circuit elements inside the window. The signal line is flagged if the calculated impedance differs from the desired impedance value.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: February 22, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy C. Nelson, Karl J. Bois
  • Patent number: 6845492
    Abstract: A computer-implemented method for adjusting signal via impedance includes identifying a signal via in a circuit design database. The signal via is flagged as having an impedance error. A window is established around the signal via, with the window lying on a single layer. Only vias in the window may be adjusted to minimize the impedance error. At least one via in the window is adjusted to minimize said impedance error.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: January 18, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark D. Frank, Jerimy C. Nelson, Karl J. Bois
  • Publication number: 20030221863
    Abstract: A data bus for a printed circuit board is disclosed having a plurality of lines separated by a substrate. A method is also disclosed for creating a bus with a reduced reflection of signal energy at the interface between the bus and a receiving agent connected to the bus. The lines in the bus include data lines and at least two strobe lines that are positioned adjacent each other to take advantage of the known impedance inherent to their dominant coupling. The bus includes separate data-line terminations and strobe-line terminations connected to the data lines and strobe lines, respectively. The separate terminations have values matched to impedances calculated from the separate sets of lines to more effectively reduce the reflected energy by more accurately matching the impedances on the lines.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 4, 2003
    Inventors: David Marshall, Karl J. Bois, Elias Gedamu
  • Patent number: 6614240
    Abstract: Determinations are made related to the presence of a predetermined material in concrete under test using previously obtained model information. In one embodiment, the predetermined material includes a chloride material and the model information is obtained using a number of cured cement specimens. The model information is stored in memory, such as in the form of a look-up table. When the concrete is being inspected, one or more magnitudes of reflections coefficients are measured and such is utilized with the model information to make determinations related to the presence of the predetermined material. In developing the model information, each of the plurality of cured cement specimens is located in a bath containing the predetermined material. The bath may be pressurized. The cured cement specimens are maintained in the bath for different, known time intervals. After the known time interval for a particular specimen, it is dried and one or more magnitudes of reflection coefficients are measured.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: September 2, 2003
    Assignee: Colorado State University Research Foundation
    Inventors: Reza Zoughi, Aaron D. Benally, Karl J. Bois, Kimberly Kurtis
  • Publication number: 20030070836
    Abstract: The present invention provides a PGA chip package that utilizes a plurality of flexible spring pins. More specifically, the spring pins, while attached between a printed circuit board and any region of the substrate, provide a bent central region that can expand or contract during operational cycles to reduce flaking, cracking, and ultimately an electrical open.
    Type: Application
    Filed: May 31, 2002
    Publication date: April 17, 2003
    Inventors: David W. Quint, Quan Qi, Karl J. Bois
  • Publication number: 20030065498
    Abstract: A method and apparatus for simulating an electronic circuit having a plurality of ports uses a digital processor to identify signal transmission characteristics associated with each of the ports. A plurality of test frequencies are selected with which to measure frequency response of the electronic circuit at each of the ports. For each of the test frequencies, a signal characteristic is identified at each of the ports in response to a sequential application of each of said test frequencies to each port. Scattering parameters corresponding to each port are extracted for each frequency based on the signal characteristics. These scattering parameters are then transformed into a time domain representation of the electronic circuit.
    Type: Application
    Filed: July 6, 2001
    Publication date: April 3, 2003
    Inventors: Karl J. Bois, David W. Quint, Peter Shaw Moldauer
  • Publication number: 20030025544
    Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 6, 2003
    Inventors: David Marshall, Karl J. Bois, David W. Quint
  • Publication number: 20020147575
    Abstract: A software method is disclosed for modeling dielectric losses in transmission lines, such as lines on a computer chip or circuit board, using a circuit simulation application, such as a SPICE program. Line resistance, self-inductance, and self-capacitance are calculated and modeled as a lumped element circuit having a resistor and an inductor connected in series, with a capacitance in parallel. A two-port scattering matrix is used to model the dielectric losses. The method uses a matrix that is related to the dielectric constant of the medium surrounding the line, the length of the line, and the frequency of the signal. The method assumes low loss conditions typical of circuit boards or integrated circuit chips, whereby the intrinsic impedance of the line is not affected by losses and the matrix is normalized to the intrinsic impedance.
    Type: Application
    Filed: February 12, 2001
    Publication date: October 10, 2002
    Inventors: Karl J. Bois, David W. Quint, Quan Qi
  • Publication number: 20020057095
    Abstract: Determinations are made related to the presence of a predetermined material in concrete under test using previously obtained model information. In one embodiment, the predetermined material includes a chloride material and the model information is obtained using a number of cured cement specimens. The model information is stored in memory, such as in the form of a look-up table. When the concrete is being inspected, one or more magnitudes of reflections coefficients are measured and such is utilized with the model information to make determinations related to the presence of the predetermined material. In developing the model information, each of the plurality of cured cement specimens is located in a bath containing the predetermined material. The bath may be pressurized. The cured cement specimens are maintained in the bath for different, known time intervals. After the known time interval for a particular specimen, it is dried and one or more magnitudes of reflection coefficients are measured.
    Type: Application
    Filed: July 16, 2001
    Publication date: May 16, 2002
    Inventors: Reza Zoughi, Aaron D. Benally, Karl J. Bois, Kimberly Kurtis