Patents by Inventor Karthik Kumar
Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12289362Abstract: A multi-tenant dynamic secure data region in which encryption keys can be shared by services running in nodes reduces the need for decrypting data as encrypted data is transferred between nodes in the data center. Instead of using a key per process/service, that is created by a memory controller when the service is instantiated (for example, MKTME), a software stack can specify that a set of processes or compute entities (for example, bit-streams) share a private key that is created and provided by the data center.Type: GrantFiled: December 26, 2020Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky
-
Patent number: 12282366Abstract: In one embodiment, an apparatus includes an interface to couple a plurality of devices of a system, the interface to enable communication according to a Compute Express Link (CXL) protocol, and a power management circuit coupled to the interface. The power management circuit may: receive, from a first device of the plurality of devices, a request according to the CXL protocol for updated power credits; identify at least one other device of the plurality of devices to provide at least some of the updated power credits; and communicate with the first device and the at least one other device to enable the first device to increase power consumption according to the at least some of the updated power credits. Other embodiments are described and claimed.Type: GrantFiled: July 26, 2021Date of Patent: April 22, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky, Dimitrios Ziakas, Rita D. Gupta
-
Publication number: 20250117673Abstract: Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate data access for a neural network inference engine having a distributed data model via dynamic management of a node associated with the neural network inference engine, the node including a database shard of a vector database.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Applicant: Intel CorporationInventors: Anjali Singhai Jain, Tamar Bar-Kanarik, Marcos Carranza, Karthik Kumar, Cristian Florin Dumitrescu, Keren Guy, Patrick Connor
-
Patent number: 12271248Abstract: System and techniques for power-based adaptive hardware reliability on a device are described herein. A hardware platform is divided into multiple partitions. Here, each partition includes a hardware component with an adjustable reliability feature. The several partitions are placed into one of multiple reliability categories. A workload with a reliability requirement is obtained and executed on a partition in a reliability category that satisfies the reliability requirements. A change in operating parameters for the device is detected and the adjustable reliability feature for the partition is modified based on the change in the operating parameters of the device.Type: GrantFiled: June 25, 2021Date of Patent: April 8, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Marcos E. Carranza, Cesar Martinez-Spessot, Mustafa Hajeer
-
Publication number: 20250103965Abstract: An apparatus includes a host interface, a network interface, and programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors are to implement network interface functionality and are to receive a prompt directed to an artificial intelligence (AI) model hosted by a host device communicably coupled to the host interface, apply a prompt tuning model to the prompt to generate an initial augmented prompt, compare the initial augmented prompt for a match with stored data of a prompt augmentation tracking table comprising real-time datacenter trend data and cross-network historical augmentation data from programmable network interface devices in a datacenter hosting the apparatus, generate, in response to identification of the match with the stored data, a final augmented prompt based on the match, and transmit the final augmented prompt to the AI model.Type: ApplicationFiled: December 6, 2024Publication date: March 27, 2025Applicant: Intel CorporationInventors: Karthik Kumar, Marcos Carranza, Thomas Willhalm, Patrick Connor
-
Publication number: 20250097306Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QOS pre-allocation; and automatic QoS migration across edge computing nodes.Type: ApplicationFiled: September 24, 2024Publication date: March 20, 2025Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G. Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
-
Patent number: 12254337Abstract: Techniques for expanded trusted domains are disclosed. In the illustrative embodiment, a trusted domain can be established that includes hardware components from a processor as well as an off-load device. The off-load device may provide compute resources for the trusted domain. The trusted domain can be expanded and contracted on-demand, allowing for a flexible approach to creating and using trusted domains.Type: GrantFiled: September 24, 2021Date of Patent: March 18, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Ravi L. Sahita, Marcos E. Carranza
-
Patent number: 12253948Abstract: Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory.Type: GrantFiled: November 9, 2020Date of Patent: March 18, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky, Zhongyan Lu, Thomas Willhalm
-
Patent number: 12254361Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic Application Programming Interface (API) contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies. The selected API technology is determined to be different than the first API technology. Based on the first contract, a second contract is dynamically generated that specifies an intermediate API that makes use of the selected API technology. A second sidecar of the destination microservice is caused to generate the intermediate API and connect the intermediate API to the first API.Type: GrantFiled: December 15, 2023Date of Patent: March 18, 2025Assignee: Intel CorporationInventors: Marcos Carranza, Cesar Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
-
Publication number: 20250086284Abstract: An apparatus includes a host interface, a network interface, and a programmable circuitry communicably coupled to the host interface and the network interface. The programmable circuitry can include one or more processors to implement network interface functionality, and a discrete trusted platform module (dTPM) to enable the one or more processors to establish a secure boot mechanism for the apparatus, wherein the one or more processors are to instantiate a virtual TPM (vTPM) manager that is associated with the dTPM, the vTPM manager to host vTPM instances corresponding to one or more virtualized environments hosted on at least one of the programmable circuitry or a host device communicable coupled to the apparatus.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Applicant: Intel CorporationInventors: Marcos Carranza, Dario Oliver, Mateo Guzman, Mariano Ortega De Mues, Cesar Martinez-Spessot, Karthik Kumar, Carolyn Wyborny, Yashaswini Raghuram Prathivadi Bhayankaram
-
Publication number: 20250083807Abstract: An apparatus for aircraft propulsion includes a propeller and a hybrid-cooled electric engine mounted to a support structure and configured to rotate the propeller. The electric engine is located in an enclosure, with a first heat transfer element thermally coupled to the electric engine via a fluid flow path, partially located outside the enclosure. A second heat transfer element, integral to or thermally coupled to the electric engine, provides air cooling. Both heat transfer elements are housed within the aircraft's support structure. At least one air inlet on the upper side of the support structure receives propeller downwash. A first cooling path directs a portion of the downwash from the air inlet to the first heat transfer element, and a first air outlet exhausts the downwash.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Applicant: Archer Aviation Inc.Inventors: Karthik Kumar BODLA, Bharat TULSYAN, Christopher M. HEATH, Kerry MANNING, Alan D. TEPE
-
Publication number: 20250086424Abstract: Deployment of resources utilizing improved mixture of experts processing is described. An example of an apparatus includes one or more network ports; one or more direct memory access (DMA) engines; and circuitry for mixture of experts (MoE) processing in the network, wherein the circuitry includes at least circuitry to track routing of tokens in MoE processing, prediction circuitry to generate predictions regarding MoE processing, including predicting future token loads for MoE processing, and routing management circuitry to manage the routing of the tokens in MoE processing based at least in part on the predictions regarding the MoE processing.Type: ApplicationFiled: November 20, 2024Publication date: March 13, 2025Applicant: Intel CorporationInventors: Karthik Kumar, Marcos Carranza, Patrick Connor
-
Publication number: 20250086123Abstract: In an embodiment, network device apparatus is provided that includes packet processing circuitry to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request, and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, may cause transmission of the memory access request to the different device. The memory access request may comprise an identifier of a requester of the memory access request and the identifier may comprise a Process Address Space identifier (PASID).Type: ApplicationFiled: September 24, 2024Publication date: March 13, 2025Applicant: Intel CorporationInventors: Karthik KUMAR, Francesc GUIM BERNAT
-
Patent number: 12240599Abstract: A VTOL aircraft includes a plurality of lift propellers configured to rotated by lift motors to provide vertical thrust during takeoff, landing and hovering operations. The lift propellers are configured to generate a cooling airflow to cool the lift motors during use. During a cruise operation when the VTOL aircraft is in forward motion, the lift propellers may be stowed in a stationary position. Therefore, the cooling airflow may be reduced or eliminated when it is not needed.Type: GrantFiled: February 2, 2023Date of Patent: March 4, 2025Assignee: Archer Aviation Inc.Inventors: Karthik Kumar Bodla, Bharat Tulsyan, Christopher M. Heath, Kerry Manning, Alan D. Tepe
-
Publication number: 20250071037Abstract: Management of data transfer for network operation is described. An example of an apparatus includes one or more network interfaces and a circuitry for management of data transfer for a network, wherein the circuitry for management of data transfer includes at least circuitry to analyze a plurality of data elements transferred on the network to identify data elements that are delayed or missing in transmission on the network, circuitry to determine one or more responses to delayed or missing data on the network, and circuitry to implement one or more data modifications for delayed or missing data on the network, including circuitry to provide replacement data for the delayed or missing data on the network.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: Intel CorporationInventors: Daniel Biederman, Patrick Connor, Karthik Kumar, Marcos Carranza, Anjali Singhai Jain
-
Publication number: 20250068457Abstract: An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Applicant: Intel CorporationInventors: Marcos Carranza, Karthik Kumar, Mariano Ortega De Mues, Mateo Guzman, Patrick Connor, Cesar Martinez-Spessot
-
Publication number: 20250068438Abstract: Described herein are technique to enable the autonomous generation of configurations for a network environment, including but not limited to an edge network of a datacenter. Additional embodiments include prompt-based generation of network and device configurations and neural network based systems for adaptive network management.Type: ApplicationFiled: November 13, 2024Publication date: February 27, 2025Applicant: Intel CorporationInventors: Mateo Guzman, Marcos Carranza, Daniel Biederman, Chihjen Chang, Jeremy Petsinger, Yadong Li, Mitu Aggarwal, Suyog Kulkarni, Mariano Ortega de Mues, Rajesh Poornachandran, Cesar Martinez, Mats Agerstam, Francesc Guim Bernat, Karthik Kumar, Usharani Ayyalasomayajula
-
Patent number: 12231487Abstract: Methods and apparatus for scale out hardware-assisted tracing schemes for distributed and scale-out applications. In connection with execution of one or more applications using a distributed processing environment including multiple compute nodes, telemetry and tracing data are obtained using hardware-based logic on the compute nodes. Processes associated with applications are identified, as well as the compute nodes on which instances of the processes are executed. Process instances are associated with process application space identifiers (PASIDs), while processes used for an application are associating with a global group identifier (GGID) that serves as an application ID. The PASIDs and GGIDs are used to store telemetry and/or tracing data on the compute nodes and/or forward such data to a tracing server in a manner that enables telemetry and/or tracing data to be aggregated on an application basis.Type: GrantFiled: February 13, 2020Date of Patent: February 18, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Patrick Kutch, Trevor Cooper, Timothy Verrall, Karthik Kumar
-
Publication number: 20250053423Abstract: Compressed configuration data may be read from a non-volatile memory of a computing device, decompressed, and used to configure circuitry of the computing device. The decompressed configuration data may be in the form of key-value pairs. A lookup table of most frequently occurring values in the original or uncompressed configuration data may be used to determine the values.Type: ApplicationFiled: August 10, 2023Publication date: February 13, 2025Inventors: Karthik KUMAR RAO, Omesh Kumar HANDA, Suhrid BHATT
-
Patent number: 12223371Abstract: Systems and methods for inter-kernel communication using one or more semiconductor devices. The semi-conductor devices include a kernel. The kernel may be in an inactive state unless performing an operation. One kernel of a first device may monitor data for an event. Once an event has occurred, the kernel sends an indication to a first inter-kernel communication circuitry. The inter-kernel communication circuitry determines an activation function of a plurality of activation functions is to be generated, generates the activation function, and transmits the activation function to a second kernel of a second device to waken and perform a function using a peer-to-peer connection.Type: GrantFiled: September 25, 2020Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Mark D. Tetreault