Patents by Inventor Karthik Kumar

Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260142865
    Abstract: Management of data bursts in network processing are described. An example of an apparatus providing management of data bursts in network processing includes circuitry to track telemetry events in operation of a network, the network including a plurality of accelerators; circuitry to predict future occurrences of data bursts, the prediction of occurrences of data bursts being based at least in part on historical telemetry data; and circuitry to transition one or more network resources from a sleep state to an operational state, the one or more network resources to be transitioned to the operational state prior to an occurrence of a predicted data burst.
    Type: Application
    Filed: November 20, 2024
    Publication date: May 21, 2026
    Applicant: Intel Corporation
    Inventors: Karthik Kumar, Marcos Carranza
  • Patent number: 12613642
    Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: April 28, 2026
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Hsing-Min Chen, Theodros Yigzaw, Russell Clapp, Saravanan Sethuraman, Patricia Mwove Shaffer
  • Patent number: 12578855
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 8, 2024
    Date of Patent: March 17, 2026
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mark Schmisseur, Thomas Willhalm
  • Patent number: 12578238
    Abstract: Technologies directed to ambient temperature and relative humidity sensing using ultrasound signals are described. One device can emit an ultrasound signal using a speaker and measure the ultrasound signal using a microphone. The device can determine, using the ultrasound signal, a signal component corresponding to a direct propagation path (DPP) between the speaker and the microphone. The device determines, using the signal component, a first sound propagation property representing a speed of the ultrasound signal along the DPP. The device determines, using the signal component across different frequency bands, second sound propagation properties, each representing a sound attenuation of the ultrasound signal along the DPP in the respective frequency band. The device determines an ambient temperature value and a relative humidity value using a regression model based on the first sound propagation property and the second sound propagation properties.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: March 17, 2026
    Assignee: Amazon Technologies, Inc.
    Inventors: Krishna Kamath Koteshwara, Berkant Tacer, Karthik Kumar, Carlos Renato Nakagawa, Sai Ravi Teja Pulugurtha, Ke Sun
  • Publication number: 20260074969
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to partition neural network models for executing at distributed Edge nodes. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions. One or more of the at least one processor circuit is to partition a neural network model into a first portion to be executed at an edge of a network and a second portion to be executed at a cloud based on a transmission metric.
    Type: Application
    Filed: October 3, 2025
    Publication date: March 12, 2026
    Applicant: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat
  • Patent number: 12572437
    Abstract: Techniques for estimating an ambient temperature based on a device power consumption are described. In an example, a system determines first data that indicates an operational temperature of a device, the first data generated by a sensor of the device. The system determines second data that indicates a power consumption of the device. Based at least in part on the first data and the second data, the system determines an ambient temperature of an external environment of the device.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: March 10, 2026
    Assignee: Amazon Technologies, Inc.
    Inventors: Karthik Kumar, Naveen Kumar, Shankar Ganapathysubramanian, Andrew Carl Brost, Cuong M. Nguyen, Sai Ravi Teja Pulugurtha, Gerald A. Welch
  • Patent number: 12566559
    Abstract: A memory request manager in a memory system registers a tenant for access to a plurality of memory devices, registers one or more service level agreement (SLA) requirements for the tenant for access to the plurality of memory devices, monitors usage of the plurality of memory devices by tenants, receives a memory request from the tenant to access a selected one of the plurality of memory devices, and allows the access when usage of the plurality of memory devices meets the one or more SLA requirements for the tenant.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 3, 2026
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Tushar Sudhakar Gohad, Mark A. Schmisseur, Thomas Willhalm
  • Publication number: 20260040493
    Abstract: Software defined cooling structures are described. A method comprises decoding sensor data from a sensor of an electronic component of an electronic device, generating a control directive to move a software defined cooling (SDC) structure of a cooling system from a first position to a second position based on the sensor data, moving the SDC structure from the first position to the second position in response to the control directive, the second position to comprise a position within a defined distance to the electronic component of the electronic device, and performing thermal management of the electronic component using the SDC structure. Other embodiments are described and claimed.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 5, 2026
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Uzair Qureshi, Marcos Carranza, Marek Piotrowski
  • Publication number: 20260032862
    Abstract: Dynamic temperature range management techniques are described. A method comprises detecting a temperature of a semiconductor die meets a first threshold value of a dynamic temperature range for the semiconductor die, generating a first control directive for a liquid cooling system to start delivery of a cooling fluid to a liquid cooling component of the semiconductor die to reduce the temperature of the semiconductor die, detecting the temperature of the semiconductor die meets a second threshold value of the dynamic temperature range for the semiconductor die, the second threshold value lower than the first threshold value of the dynamic temperature range, and generating a second control directive to stop delivery of the cooling fluid to the liquid cooling component of the semiconductor die. Other embodiments are described and claimed.
    Type: Application
    Filed: July 24, 2024
    Publication date: January 29, 2026
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Eng Kwong Lee, Chew Ching Lim, Marcos Carranza
  • Publication number: 20260032869
    Abstract: A modular computing and cooling system is described. For example, an apparatus may comprise a physical interface for a modular computing and cooling system and an electronic cooling cartridge for insertion into the physical interface and removal from the physical interface. The electronic cooling cartridge may comprise an internal electronic component, an internal cooling component for thermal management of the internal electronic component using a cooling fluid, a set of internal connectors to connect the internal electronic component and the internal cooling component to an external electronic component and an external cooling component, respectively, of the modular computing and cooling system, and a closed container encapsulating the internal electronic component, the internal cooling component, and the set of internal connectors. Other embodiments are described and claimed.
    Type: Application
    Filed: July 24, 2024
    Publication date: January 29, 2026
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Uzair Qureshi, Marcos Carranza, Marek Piotrowski
  • Publication number: 20260024568
    Abstract: Examples include techniques associated with data erase and clear operations using memory cell refresh mechanisms associated with volatile types of memory. The memory cell refresh mechanisms used for data erase and clear operations include manipulation of a refresh signal to cause volatile memory cells to be cleared or erased. The volatile memory cells to be identified as short-term memory cells.
    Type: Application
    Filed: September 30, 2025
    Publication date: January 22, 2026
    Inventors: Gurpreet Singh KALSI, Akhilesh S. THYAGATURU, Karthik KUMAR, Ajith PATCHANNA
  • Publication number: 20260010500
    Abstract: Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.
    Type: Application
    Filed: April 2, 2025
    Publication date: January 8, 2026
    Inventors: Karthik KUMAR, Susanne M. BALLE, Marcos E. CARRANZA, Sharanyan SRIKANTHAN, Ishwar AGARWAL, Patricia M. MWOVE SHAFFER, Akhilesh S. THYAGATURU, Francesc GUIM BERNAT, Thomas WILLHALM
  • Publication number: 20260003983
    Abstract: Methods, systems, and apparatus, including computer-readable storage media for validation of Infrastructure-as-Code (IaC) configurations with added context, using a language model. A validation system can receive a request to validate an IaC configuration file. The request can include the IaC configuration file to be validated, as well as identifiers for identifying the policy from which validation requirements should be used for validating the IaC configuration file. Pre-trained machine learning models for generating natural language and/or structured code output may be fine-tuned to reduce or eliminate hallucinations, vague. or incorrect output, using training examples of syntactically correct IaC configuration files. An embedding repository of syntactically correct IaC configuration files and a repository of policy documents can be queried for augmenting the prompt to the language model.
    Type: Application
    Filed: September 3, 2025
    Publication date: January 1, 2026
    Inventors: Sushant Kumar Singh, Karthik Kumar, Jashanjot Kaur, Kishore Kumar Garg, Pankhuri Saxena, Mukesh Kumar Marodia, Priyanka Tiruveedhula
  • Patent number: 12511071
    Abstract: Methods and apparatus for advanced interleaving techniques for fabric based pooling architectures. The method implemented in an environment including a switch connected to host servers and to pooled memory nodes or memory servers hosting memory pools. Memory is interleaved across the memory pools using interleaving units, with the interleaved memory mapped into a global memory address space. Applications running on the host servers are enabled to access data stored in the memory pools via memory read and write requests issued by the applications specifying address endpoints within the global memory space. The switch generates multi-cast or multiple unicast messages associated with the memory read and write requests that are sent to the pooled memory nodes or memory servers. For memory reads, the data returned from multiple memory pools is aggregated at the switch and returned to the application using one or more packets as a single response.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: December 30, 2025
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky, Marcos E. Carranza
  • Publication number: 20250379824
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for edge data prioritization. An example apparatus includes at least one memory, instructions, and processor circuitry to at least one of execute or instantiate the instructions to identify an association of a data packet with a data stream based on one or more data stream parameters included in the data packet corresponding to the data stream, the data packet associated with a first priority, execute a model based on the one or more data stream parameters to generate a model output, determine a second priority of at least one of the data packet or the data stream based on the model output, the model output indicative of an adjustment of the first priority to the second priority, and cause transmission of at least one of the data packet or the data stream based on the second priority.
    Type: Application
    Filed: May 23, 2025
    Publication date: December 11, 2025
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Marcos Carranza, Rita Wouhaybi, Cesar Martinez-Spessot
  • Patent number: 12493429
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to persistent media, and manage an endurance of the persistent media based on one or more endurance hints from an external source. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: December 9, 2025
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20250370948
    Abstract: Examples described herein relate to configuring a switch in an accelerator fabric to: monitor accesses to a memory region by one or more accelerators coupled to the accelerator fabric and report the accesses to the memory region to one or more specified accelerators coupled to the accelerator fabric. In some examples, the configuration includes a call to an application programing interface (API), a configuration file, a remote procedure call (RPC), or execution of a binary.
    Type: Application
    Filed: August 14, 2025
    Publication date: December 4, 2025
    Inventors: Marcos E. CARRANZA, Karthik KUMAR, Thomas WILLHALM, Cesar Ignacio MARTINEZ SPESSOT
  • Patent number: 12468578
    Abstract: System and techniques for infrastructure managed workload distribution are described herein. An infrastructure processing unit (IPU) receives a workload that includes a workload definition. The workload definition includes stages of the workload and a performance expectation. The IPU provides the workload, for execution, to a processing unit of a compute node to which the IPU belongs. The IPU monitors execution of the workload to determine that a stage of the workload is performing outside of the performance expectation from the workload definition. In response, the IPU modifies the execution of the workload.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: November 11, 2025
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky, Marcos E. Carranza, Rita H. Wouhaybi
  • Patent number: 12461828
    Abstract: Examples described herein relate to a network interface device that comprises circuitry, when operational, to select a platform to execute a function and based on load of the platform, selectively cause the function to execute on one or more other platforms to attempt to achieve or finish before the time-to-completion. In some examples, the circuitry is to detect progress of function execution to determine whether completion of execution of the function is predicted to not finish within the time-to-completion and cause the function to execute on one or more other platforms based on completion of execution of the function predicted to not finish within the time-to-completion. In some examples, the circuitry is to select the one or more other platforms to execute the function based on one or more of: processor computing utilization, available memory capacity, available cache capacity, network availability, or malfunction of a processor, memory, and/or cache.
    Type: Grant
    Filed: June 26, 2021
    Date of Patent: November 4, 2025
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Alexander Bachmutsky, Patrick G. Kutch, Marcos E. Carranza
  • Patent number: 12463875
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to partition neural network models for executing at distributed Edge nodes. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate power consumption estimation circuitry to estimate a computation energy consumption for executing the neural network model on a first edge node, network bandwidth determination circuitry to determine a first transmission time for sending an intermediate result from the first edge node to a second or third edge node, power consumption estimation circuitry to estimate a transmission energy consumption for sending the intermediate result to the second or the third edge node, and neural network partitioning circuitry to partition the neural network model into a first portion to be executed at the first edge node and a second portion to be executed at the second or third edge node.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 4, 2025
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat