Abstract: A network processing device connects to one or more devices in a computing node and connects to one or more other network processing devices of other computing nodes. The network processing device identifies a policy for allowing devices in other computing nodes to access a particular resource of one of the devices in its computing node. The network processing device receives an access request to access the particular resource from another network processing device and sends a request to the device hosting the particular resource based on the access request and the policy.

Abstract: The present disclosure is generally related to edge computing technologies (ECTs), communications networking, network slicing, and in particular, to techniques and technologies for providing flow-specific network slices. In particular, the present disclosure describes mechanisms that expand existing end-to-end architectures in order to include quality of service and monitoring mechanisms that connect network slicing technologies with infrastructure and/or network data center quality of service provider domains. The described mechanisms provide data center bridging to enable network, edge computing, and cloud computing domains.

Abstract: In one embodiment, an apparatus couples to a host processor over a Compute Express Link (CXL)-based link. The apparatus includes a transaction queue to queue memory transactions to be completed in an addressable memory coupled to the apparatus, a transaction cache, conflict detection circuitry to determine whether a conflict exists between memory transactions, and transaction execution circuitry. The transaction execution circuitry may access a transaction from the transaction queue, the transaction to implement one or more memory operations in the memory, store data from the memory to be accessed by the transaction operations in the transaction cache, execute operations of the transaction, including modifying data from the memory location stored in the transaction cache, and based on completion of the transaction, cause the modified data from the transaction cache to be stored in the memory.

Abstract: Techniques and mechanisms to allocate functionality of a chiplet for access by one or more processor cores which are coupled to remote processor via a network switch. In an embodiment, a composite chip communicates with the switch via a Compute Express Link (CXL) link. The switch receives capability information which identifies both a chiplet of the composite chip, and a functionality which is available from a resource of that chiplet. Based on the capability information, the switch provides an inventory of chiplet resources. In response to an allocation request, the switch accesses the inventory to identify whether a suitable chiplet resource is available. Based on the access, the switch configures a chip to enable an allocation of a chiplet resource. In another embodiment, the chiplet resource is allocated at a sub-processor level of granularity, and disables access to the chiplet resource by one or more local processor cores.

Abstract: Methods and apparatus for hardware support for low latency microservice deployments in switches. A switch is communicatively coupled via a network or fabric to a plurality of platforms configured to implement one or more microservices. The microservices are used to perform a distributed workload, job, or task as defined by a corresponding graph representation of the microservices including vertices (also referred to as nodes) associated with microservices and edges defining communication between microservices. The graph representation also defines dependencies between microservices. The switch is configured to schedule execution of the graph of microservices on the plurality of platforms, including generating an initial schedule that is dynamically revised during runtime in consideration of performance telemetry data for the microservices received from the platforms and network/fabric utilization monitored onboard the switch.

Abstract: In a server system, a host computing platform can have a processing unit separate from the host processor to detect and respond to failure of the host processor. The host computing platform includes a memory to store data for the host processor. The processing unit has an interface to the host processor and the memory and an interface to a network external to the host processor and has access to the memory. In response to detection of failure of the host processor, the processing unit migrates data from the memory to another memory or storage.

Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.

Abstract: Management of data bursts in network processing are described. An example of an apparatus providing management of data bursts in network processing includes circuitry to track telemetry events in operation of a network, the network including a plurality of accelerators; circuitry to predict future occurrences of data bursts, the prediction of occurrences of data bursts being based at least in part on historical telemetry data; and circuitry to transition one or more network resources from a sleep state to an operational state, the one or more network resources to be transitioned to the operational state prior to an occurrence of a predicted data burst.

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.

Abstract: Technologies directed to ambient temperature and relative humidity sensing using ultrasound signals are described. One device can emit an ultrasound signal using a speaker and measure the ultrasound signal using a microphone. The device can determine, using the ultrasound signal, a signal component corresponding to a direct propagation path (DPP) between the speaker and the microphone. The device determines, using the signal component, a first sound propagation property representing a speed of the ultrasound signal along the DPP. The device determines, using the signal component across different frequency bands, second sound propagation properties, each representing a sound attenuation of the ultrasound signal along the DPP in the respective frequency band. The device determines an ambient temperature value and a relative humidity value using a regression model based on the first sound propagation property and the second sound propagation properties.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to partition neural network models for executing at distributed Edge nodes. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions. One or more of the at least one processor circuit is to partition a neural network model into a first portion to be executed at an edge of a network and a second portion to be executed at a cloud based on a transmission metric.

Abstract: Techniques for estimating an ambient temperature based on a device power consumption are described. In an example, a system determines first data that indicates an operational temperature of a device, the first data generated by a sensor of the device. The system determines second data that indicates a power consumption of the device. Based at least in part on the first data and the second data, the system determines an ambient temperature of an external environment of the device.

Abstract: A memory request manager in a memory system registers a tenant for access to a plurality of memory devices, registers one or more service level agreement (SLA) requirements for the tenant for access to the plurality of memory devices, monitors usage of the plurality of memory devices by tenants, receives a memory request from the tenant to access a selected one of the plurality of memory devices, and allows the access when usage of the plurality of memory devices meets the one or more SLA requirements for the tenant.

Abstract: Software defined cooling structures are described. A method comprises decoding sensor data from a sensor of an electronic component of an electronic device, generating a control directive to move a software defined cooling (SDC) structure of a cooling system from a first position to a second position based on the sensor data, moving the SDC structure from the first position to the second position in response to the control directive, the second position to comprise a position within a defined distance to the electronic component of the electronic device, and performing thermal management of the electronic component using the SDC structure. Other embodiments are described and claimed.

Abstract: Dynamic temperature range management techniques are described. A method comprises detecting a temperature of a semiconductor die meets a first threshold value of a dynamic temperature range for the semiconductor die, generating a first control directive for a liquid cooling system to start delivery of a cooling fluid to a liquid cooling component of the semiconductor die to reduce the temperature of the semiconductor die, detecting the temperature of the semiconductor die meets a second threshold value of the dynamic temperature range for the semiconductor die, the second threshold value lower than the first threshold value of the dynamic temperature range, and generating a second control directive to stop delivery of the cooling fluid to the liquid cooling component of the semiconductor die. Other embodiments are described and claimed.

Abstract: A modular computing and cooling system is described. For example, an apparatus may comprise a physical interface for a modular computing and cooling system and an electronic cooling cartridge for insertion into the physical interface and removal from the physical interface. The electronic cooling cartridge may comprise an internal electronic component, an internal cooling component for thermal management of the internal electronic component using a cooling fluid, a set of internal connectors to connect the internal electronic component and the internal cooling component to an external electronic component and an external cooling component, respectively, of the modular computing and cooling system, and a closed container encapsulating the internal electronic component, the internal cooling component, and the set of internal connectors. Other embodiments are described and claimed.

Abstract: Examples include techniques associated with data erase and clear operations using memory cell refresh mechanisms associated with volatile types of memory. The memory cell refresh mechanisms used for data erase and clear operations include manipulation of a refresh signal to cause volatile memory cells to be cleared or erased. The volatile memory cells to be identified as short-term memory cells.

Abstract: Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.

Abstract: Methods, systems, and apparatus, including computer-readable storage media for validation of Infrastructure-as-Code (IaC) configurations with added context, using a language model. A validation system can receive a request to validate an IaC configuration file. The request can include the IaC configuration file to be validated, as well as identifiers for identifying the policy from which validation requirements should be used for validating the IaC configuration file. Pre-trained machine learning models for generating natural language and/or structured code output may be fine-tuned to reduce or eliminate hallucinations, vague. or incorrect output, using training examples of syntactically correct IaC configuration files. An embedding repository of syntactically correct IaC configuration files and a repository of policy documents can be queried for augmenting the prompt to the language model.