Patents by Inventor Karthik Kumar

Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11994932
    Abstract: Methods and apparatus for platform ambient data management schemes for tiered architectures. A platform including one or more CPUs coupled to multiple tiers of memory comprising various types of DIMMs (e.g., DRAM, hybrid, DCPMM) is powered by a battery subsystem receiving input energy harvested from one or more green energy sources. Energy threshold conditions are detected, and associated memory reconfiguration is performed. The memory reconfiguration may include but is not limited to copying data between DIMMs (or memory ranks on the DIMMS in the same tier, copying data between a first type of memory to a second type of memory on a hybrid DIMM, and flushing dirty lines in a DIMM in a first memory tier being used as a cache for a second memory tier. Following data copy and flushing operations, the DIMMs and/or their memory devices are powered down and/or deactivated.
    Type: Grant
    Filed: June 21, 2020
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat
  • Patent number: 11994997
    Abstract: Systems, apparatuses and methods may provide for a memory controller to manage quality of service enforcement and migration between local and pooled memory. A memory controller may include logic to communicate with a local memory and with a pooled memory controller to track memory page usage on a per application basis, instruct the pooled memory controller to perform a quality of service enforcement in response to a determination that an application is latency bound or bandwidth bound, wherein the determination that the application is latency bound or bandwidth bound is based on a cycles per instruction determination, and instruct a Direct Memory Access engine to perform a migration from a remote memory to the local memory in response to a determination that the quality of service cannot be enforced.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 28, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Mark A. Schmisseur
  • Patent number: 11983437
    Abstract: In one embodiment, an apparatus includes: a first queue to store requests that are guaranteed to be delivered to a persistent memory; a second queue to store requests that are not guaranteed to be delivered to the persistent memory; a control circuit to receive the requests and to direct the requests to the first queue or the second queue; and an egress circuit coupled to the first queue to deliver the requests stored in the first queue to the persistent memory even when a power failure occurs. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Donald Faw, Thomas Willhalm
  • Publication number: 20240143505
    Abstract: Methods and apparatus for dynamic selection of super queue size for CPUs with higher number of cores. An apparatus includes a plurality of compute modules, each module including a plurality of processor cores with integrated first level (L1) caches and a shared second level (L2) cache, a plurality of Last Level Caches (LLCs) or LLC blocks and a plurality of memory interface blocks interconnect via a mesh interconnect. A compute module is configured to arbitrate access to the shared L2 cache and enqueue L2 cache misses in a super queue (XQ). The compute module further is configured to dynamically adjust the size of the XQ during runtime operations. The compute module tracks parameters comprising an L2 miss rate or count and LLC hit latency and adjusts the XQ size as a function of these parameters. A lookup table using the L2 miss rate/count and LLC hit latency may be implemented to dynamically select the XQ size.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 2, 2024
    Inventors: Amruta MISRA, Ajay RAMJI, Rajendrakumar CHINNAIYAN, Chris MACNAMARA, Karan PUTTANNAIAH, Pushpendra KUMAR, Vrinda KHIRWADKAR, Sanjeevkumar Shankrappa ROKHADE, John J. BROWNE, Francesc GUIM BERNAT, Karthik KUMAR, Farheena Tazeen SYEDA
  • Publication number: 20240146639
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to reduce emissions in guided network environments. An apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to collect data from respective network nodes corresponding to a request to access information, predict an emission of accessing the information via the respective network nodes using the data, and select a network path including at least one of the network nodes based on the predicted emission.
    Type: Application
    Filed: December 21, 2023
    Publication date: May 2, 2024
    Inventors: Francesc Guim Bernat, Manish Dave, Karthik Kumar, Akhilesh S. Thyagaturu, Matthew Henry Birkner, Adrian Hoban
  • Patent number: 11972291
    Abstract: An apparatus and method for conditional quality of service in a processor. For example, one embodiment of a processor comprises: a plurality of processor resources to be allocated to a plurality of executed processes in accordance with a set of quality of service (QoS) rules; and conditional quality of service (QoS) circuitry/logic to monitor usage of the plurality of processor resources by the plurality of processes and to responsively modify an allocation of a first processor resource for a first process in response to detecting a first threshold value being reached in a second resource allocated to the first process.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim, Karthik Kumar, Mustafa Hajeer, Tushar Gohad
  • Publication number: 20240134726
    Abstract: A method is described. The method includes invoking one of more functions from a set of API functions that expose the current respective cooling states of different, respective cooling devices for different components of a hardware platform. The method includes orchestrating concurrent execution of multiple applications on the hardware platform in view of the current respective cooling states. The method includes, in order to prepare the hardware platform for the concurrent execution of the multiple applications, prior to the concurrent execution of the multiple applications, sending one or more commands to the hardware platform to change a cooling state of at least one of the cooling devices.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 25, 2024
    Inventors: Akhilesh S. THYAGATURU, Francesc GUIM BERNAT, Karthik KUMAR, Adrian HOBAN, Marek PIOTROWSKI
  • Publication number: 20240134432
    Abstract: A method is claimed. The method includes receiving information associated with a software application's workflow. The method includes receiving information that describes a platform's current power consumption state and current thermal state. The method includes selecting platform components to support execution of the workflow. The method includes prior to execution of the workflow upon the selected platform components, estimating a thermal impact to the platform's current thermal state as a consequence of the workflow's execution upon the selected platform components. The method includes determining a change to be made to a thermal cooling system of the platform in response to the estimating and causing the change to be made to the thermal cooling system prior to execution of at least a portion of the workflow on the platform.
    Type: Application
    Filed: December 12, 2023
    Publication date: April 25, 2024
    Inventors: Akhilesh S. THYAGATURU, Francesc GUIM BERNAT, Karthik KUMAR, Jonathan KYLE, Marek PIOTROWSKI
  • Publication number: 20240134436
    Abstract: An integrated circuit (IC) device, such as a system on chip, includes a plurality of hardware circuitry components and a power delivery network to delivery power to the plurality of hardware circuitry elements. The power delivery network has a plurality of integrated switches and a corresponding data plane to couple the plurality of switches to a controller on the IC device. The controller sends signals on the control plane of the power delivery network to granularly select which of the plurality of hardware circuitry elements to power-gate and may do so at the direction of a software system.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Akhilesh Thyagaturu, Karthik Kumar, Francesc Guim Bernat, Manish Dave, Xiangyang Zhuang
  • Publication number: 20240126579
    Abstract: A server platform in a cloud computing system is determined to be in an unused state and a request from a remote computing system outside the data center system is received to control hardware of at least one of the server platforms of the cloud computing systems. A bare-metal-as-is (BMAI) session is initiated for the remote computing system to use the server platform based on the unused state, wherein exclusive control of at least a portion of hardware of the server platform is temporarily handed over to the remote computing system in the BMAI session. Control of the portion of the hardware of the server platform is reclaimed based on an end of the BMAI session.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Akhilesh Thyagaturu, Jonathan L. Kyle, Mohit Kumar Garg, Karthik Kumar, Francesc Guim Bernat
  • Publication number: 20240126606
    Abstract: Data that is to be processed by a particular service executed by a first edge computing device in an application, is analyzed to determine characteristics of the data. An opportunity to replicate the particular service on a plurality of edge computing devices is determined based on characteristics of the data. A second edge computing device is determined to be available to execute a replicated instance of the particular service. Replication of the particular service is initiated on a plurality of edge computing devices including the second edge computing device. An output of an instance of the particular service executed on the first edge computing device and an output of the replicated instance of the particular service executed on the second edge computing device are combined to form a single output for the particular service.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Akhilesh Thyagaturu, Jonathan L. Kyle, Karthik Kumar, Francesc Guim Bernat, Mohit Kumar Garg
  • Publication number: 20240116627
    Abstract: A VTOL aircraft includes a plurality of lift propellers configured to rotated by lift motors to provide vertical thrust during takeoff, landing and hovering operations. The lift propellers are configured to generate a cooling airflow to cool the lift motors during use. During a cruise operation when the VTOL aircraft is in forward motion, the lift propellers may be stowed in a stationary position. Therefore, the cooling airflow may be reduced or eliminated when it is not needed.
    Type: Application
    Filed: February 2, 2023
    Publication date: April 11, 2024
    Applicant: Archer Aviation, Inc.
    Inventors: Karthik Kumar BODLA, Bharat TULSYAN, Christopher M. HEATH, Kerry MANNING, Alan D. TEPE
  • Publication number: 20240113954
    Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 4, 2024
    Inventors: Francesc GUIM BERNAT, Susanne M. BALLE, Rahul KHANNA, Sujoy SEN, Karthik KUMAR
  • Publication number: 20240111615
    Abstract: Embodiments described herein are generally directed to the use of sidecars to perform dynamic API contract generation and conversion. In an example, a first sidecar of a source microservice intercepts a first call to a first API exposed by a destination microservice. The first call makes use of a first API technology specified by a first contract and is originated by the source microservice. An API technology is selected from multiple API technologies. The selected API technology is determined to be different than the first API technology. Based on the first contract, a second contract is dynamically generated that specifies an intermediate API that makes use of the selected API technology. A second sidecar of the destination microservice is caused to generate the intermediate API and connect the intermediate API to the first API.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Marcos Carranza, Cesar Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
  • Publication number: 20240103743
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to store data based on an environmental impact of a storage device. An example apparatus to store data, the apparatus includes programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine a first environmental impact associated with storing the data in a first storage device, determine a second environmental impact associated with storing the data in a second storage device, and cause the data to be stored in one of the first storage device or the second storage device based on the first environmental impact and the second environmental impact.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Francesc Guim Bernat, Karthik Kumar, Akhilesh S. Thyagaturu, Mario Jose Divan, Matthew Henry Birkner
  • Publication number: 20240103861
    Abstract: An apparatus is described. The apparatus includes a memory module. The memory module includes a memory. The memory module includes function execution circuitry. The function execution circuitry is configurable to execute a producer function and a consumer function of a multi-function process. The memory module includes an interface to be coupled to a memory controller.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Inventors: Akhilesh S. THYAGATURU, Francesc GUIM BERNAT, Karthik KUMAR, Mohit Kumar GARG
  • Publication number: 20240086341
    Abstract: Methods, apparatus and systems for adaptive fabric allocation for local and remote emerging memories-based prediction schemes. In conjunction with performing memory transfers between a compute host and memory device connected via one or more interconnect segments, memory read and write traffic is monitored for at least one interconnect segment having reconfigurable upstream lanes and downstream lanes. Predictions of expected read and write bandwidths for the at least one interconnect segment are then made. Based on the expected read and write bandwidths, the upstream lanes and downstream lanes are dynamically reconfigured. The interconnect segments include interconnect links such as Compute Exchange Link (CXL) flex buses and memory channels for local memory implementations, and fabric links for remote memory implementations. For local memory, management messages may be used to provide telemetry information containing the expected read and write bandwidths.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 14, 2024
    Inventors: Benjamin Graniello, Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm
  • Publication number: 20240086291
    Abstract: An apparatus comprising first circuitry to process a request generated by a first device, the request specifying a memory address range of a second device to monitor for errors; and second circuitry to, based on a determination that a read request targets the memory address range of the second device, compare first data read from the second device with second data read from a memory to determine whether an error has occurred.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Amruta Misra
  • Patent number: 11922227
    Abstract: Technologies for providing efficient migration of services include a server device. The server device includes compute engine circuitry to execute a set of services on behalf of a terminal device and migration accelerator circuitry. The migration accelerator circuitry is to determine whether execution of the services is to be migrated from an edge station in which the present server device is located to a second edge station in which a second server device is located, determine a prioritization of the services executed by the server device, and send, in response to a determination that the services are to be migrated and as a function of the determined prioritization, data utilized by each service to the second server device of the second edge station to migrate the services. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Ignacio Astilleros Diez, Timothy Verrall, Ned M. Smith
  • Patent number: 11907136
    Abstract: An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Ginger H. Gilsdorf, Karthik Kumar, Mark A. Schmisseur, Thomas Willhalm, Francesc Guim Bernat