Patents by Inventor Karthik Kumar
Karthik Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12164977Abstract: An apparatus comprising a network interface controller comprising a queue for messages for a thread executing on a host computing system, wherein the queue is dedicated to the thread; and circuitry to send a notification to the host computing system to resume execution of the thread when a monitoring rule for the queue has been triggered.Type: GrantFiled: December 23, 2020Date of Patent: December 10, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Patrick G. Kutch, Alexander Bachmutsky, Nicolae Octavian Popovici
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Publication number: 20240407142Abstract: Hybrid and adaptive cooling systems are described. A method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. Other embodiments are described and claimed.Type: ApplicationFiled: August 9, 2024Publication date: December 5, 2024Applicant: INTEL CORPORATIONInventors: Francesc Guim Bernat, Karthik Kumar, Uzair Qureshi, Marcos Carranza, Marek Piotrowski
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Publication number: 20240396852Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.Type: ApplicationFiled: August 1, 2024Publication date: November 28, 2024Applicant: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark A. Schmisseur, Timothy Verrall
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Publication number: 20240385884Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to estimate workload complexity. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate payload interface circuitry to extract workload objective information and service level agreement (SLA) criteria corresponding to a workload, and acceleration circuitry to select a pre-processing model based on (a) the workload objective information and (b) feedback corresponding to workload performance metrics of at least one prior workload execution iteration, execute the pre-processing model to calculate a complexity metric corresponding to the workload, and select candidate resources based on the complexity metric.Type: ApplicationFiled: December 23, 2021Publication date: November 21, 2024Inventors: Karthik Kumar, Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Zhongyan Lu
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Patent number: 12132825Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.Type: GrantFiled: December 23, 2021Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Rajesh Poornachandran, Kapil Sood, Tarun Viswanathan, John J. Browne, Patrick Kutch
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Patent number: 12132805Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.Type: GrantFiled: December 3, 2021Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Petar Torre, Ned Smith, Brinda Ganesh, Evan Custodio, Suraj Prabhakaran
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Patent number: 12130754Abstract: Examples described herein relate to a network device apparatus that includes a packet processing circuitry configured to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, cause transmission of the memory access request to the different device. In some examples, the memory access request comprises an identifier of a requester of the memory access request and the identifier comprises a Process Address Space identifier (PASID) and wherein the configuration that a redirection operation is permitted to be performed for a memory access request is based at least on the identifier.Type: GrantFiled: August 17, 2020Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Karthik Kumar, Francesc Guim Bernat
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Patent number: 12132790Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.Type: GrantFiled: July 28, 2022Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
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Patent number: 12132664Abstract: Example edge gateway circuitry to schedule service requests in a network computing system includes: gateway-level hardware queue manager circuitry to: parse the service requests based on service parameters in the service requests; and schedule the service requests in a queue based on the service parameters, the service requests received from client devices; and hardware queue manager communication interface circuitry to send ones of the service requests from the queue to rack-level hardware queue manager circuitry in a physical rack, the ones of the service requests corresponding to functions as a service provided by resources in the physical rack.Type: GrantFiled: December 19, 2022Date of Patent: October 29, 2024Assignee: INTEL CORPORATIONInventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ignacio Astilleros Diez, Timothy Verrall
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Publication number: 20240353915Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to perform dynamic function control. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to parse a packet for a function directive, activate a function associated with the function directive based on a type of the function directive being associated with an activation instruction, disable the function associated with the function directive based on the type of the function directive being associated with a deactivation instruction, and publish an active function list (AFL) and a passive function list (PFL) based on the type of the function directive.Type: ApplicationFiled: July 3, 2024Publication date: October 24, 2024Inventors: Akhilesh S. Thyagaturu, Francesc Guim Bernat, Karthik Kumar, Stephen Thomas Palermo, John J. Browne
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Patent number: 12120012Abstract: A device of a service coordinating entity includes communications circuitry to communicate with a plurality of access networks via a corresponding plurality of network function virtualization (NFV) instances, processing circuitry, and a memory device. The processing circuitry is to perform operations to monitor stored performance metrics for the plurality of NFV instances. Each of the NFV instances is instantiated by a corresponding scheduler of a plurality of schedulers on a virtualization infrastructure of the service coordinating entity. A plurality of stored threshold metrics is retrieved, indicating a desired level for each of the plurality of performance metrics. A threshold condition is detected for at least one of the performance metrics for an NF V instance of the plurality of NFV instances, based on the retrieved plurality of threshold metrics. A hardware resource used by the NFV instance to communicate with an access network is adjusted based on the detected threshold condition.Type: GrantFiled: August 19, 2021Date of Patent: October 15, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Andrew J. Herdrich, Karthik Kumar, Felipe Pastor Beneyto, Edwin Verplanke, Rashmin Patel, Monica Kenguva, Brinda Ganesh, Alexander Vul, Ned M. Smith
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Patent number: 12120175Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.Type: GrantFiled: March 7, 2022Date of Patent: October 15, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Ned Smith, Thomas Willhalm, Karthik Kumar, Timothy Verrall
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Publication number: 20240320483Abstract: Disclosed is a method for identifying multi-level hierarchical relationships between data elements of a document, the method comprising receiving a plurality of sample documents each having a plurality of data elements arranged in a multi-level hierarchical data structure; classifying each of the plurality of data elements into a key entity field or a key field value based on a hierarchical relationship therebetween; identifying key entity fields, from among the classified key entity field of the plurality of data elements, having the hierarchical relationship therebetween; pairing the key entity field, with a corresponding key field value or an identified key entity field, to form a training dataset; and employing the training dataset on a neural network framework, having at least one of a textual modality or a visual modality, to identify the multi-level hierarchical relationships between the data elements of the document.Type: ApplicationFiled: March 21, 2023Publication date: September 26, 2024Applicant: Quantiphi, IncInventors: Bhaskar Kalita, Karthik Kumar Veldandi, Jeevan Prakash, Alok Kumar Garg, Sagar Kewalramani
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Patent number: 12088507Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.Type: GrantFiled: July 11, 2022Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark A. Schmisseur, Timothy Verrall
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Publication number: 20240273120Abstract: Systems, apparatuses and methods include technology that identifies first data that is autonomously generated, where the first data is associated with a first source. The technology may further determine that the first data is to be marked with an indication that the first data is associated with the first source, generate an identifier associated with the first data based on the first data being determined to be marked, where the identifier indicates that the first data is associated with the first source, and store the identifier to an entry in a storage that is remotely accessible.Type: ApplicationFiled: March 14, 2024Publication date: August 15, 2024Inventors: Francesc Guim Bernat, Karthik Kumar, Akhilesh S. Thyagaturu, Marcos Carranza, Rajesh Poornachandran
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Patent number: 12063280Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to obtain provenance metadata for a microservice from a local blockchain of provenance metadata maintained for the hardware resource executing a task performed by the microservice, the provenance metadata comprising identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and an operating state of a sidecar of the microservice during the task; access one or more policies established for the microservice; analyze the provenance metadata with respect to the one or more policies to identify if there is a violation of the one or more policies; and generate one or more evaluation metrics based on whether the violation of the one or more policies is identified.Type: GrantFiled: August 25, 2023Date of Patent: August 13, 2024Assignee: INTEL CORPORATIONInventors: Rajesh Poornachandran, Vincent Zimmer, Subrata Banik, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
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Patent number: 12063223Abstract: Systems and methods for implementing a system for analyzing large amounts of event data to determine any potential security threats or anomalies. Event data may be obtained and processed. The processed event data may be analyzed to detect any potential security threats or anomalies.Type: GrantFiled: December 11, 2019Date of Patent: August 13, 2024Assignee: Amazon Technologies, Inc.Inventors: Joshua Haycraft, Vignesh Janakiraman, Jessica Erin Clark, Pradeep Ramarao, Karthik Kumar Odapally
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Patent number: 12058036Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.Type: GrantFiled: May 17, 2022Date of Patent: August 6, 2024Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj Ramanujan, Brian Slechta
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Publication number: 20240256685Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. An embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. Other embodiments are disclosed and claimed.Type: ApplicationFiled: April 8, 2024Publication date: August 1, 2024Applicant: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Mark Schmisseur, Thomas Willhalm
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Publication number: 20240248633Abstract: Various examples of the present disclosure relate to apparatuses, devices, methods, and computer programs for providing and processing information characterizing a non-uniform memory architecture. An apparatus for a computer system comprises processing circuitry to determine a presence of one or more memory devices connected to at least one processor of the computer system via a serial communication-based processor-to-memory interface, the one or more memory devices being part of a non-uniform memory architecture used by the computer system, determine at least one characteristic for the one or more memory devices by estimating or measuring a performance of the one or more memory devices as observed by the at least one processor, and provide information on the at least one characteristic of the one or more memory devices as part of information characterizing the non-uniform memory architecture.Type: ApplicationFiled: September 29, 2023Publication date: July 25, 2024Inventors: Francesc GUIM BERNAT, Karthik KUMAR, Marcos CARRANZA, Rajesh POORNACHANDRAN, Thomas WILLHALM