Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar includes a reference clock, a phase locked loop (PLL), a pulse generator, a counter, a chirp ramp control circuit, and a synchronization state machine. The reference clock generates a reference clock signal. The PLL generates a feedback clock signal in response to the reference clock signal, and an output signal in response to the feedback clock signal. The pulse generator outputs a chirp start pulse in response to the reference clock signal. The counter increments a count in response to the feedback clock signal. The synchronization state machine provides a chirp ramp signal to a chirp ramp control circuit in response to the reference clock signal, the feedback clock signal, the chirp start pulse, and the count. The chirp ramp control circuit causes the PLL to ramp a frequency of the output signal in response to the chirp ramp signal.

Abstract: An example radar system includes transmit, receive and processing circuitry. In operation, the radar system transmits first and second sets of chirp signals in which each chirp signal of the first set of chirp signals has an induced phase shift, receives reflected signals based on the transmitted first and second sets of chirp signals, and generates respective first and second sets of digital signals. Fourier Transform (FT) operations are performed on the first and second sets of digital signals to generate first and second arrays, respectively. The radar system identifies a first peak in the first array and a second peak in the second array representing an object in a field of view. The first and second peaks are at corresponding positions in the first and second arrays, respectively. The radar system then compares the phases of the first and second peaks to determine an actual phase shift for the induced phase shift.

Abstract: In described examples, an integrated circuit (IC) includes a fast Fourier transform (FFT) engine, a first memory, a second memory, a conjugate symmetric combiner (CSC), and a control circuit coupled to control them. The first and second memories are coupled to the FFT engine, and the CSC is coupled to the first and second memories and the FFT engine. The FFT engine receives and processes a first stream of samples to generate a second stream of samples. In a first phase, the FFT engine provides a first portion of the second stream of samples to the first memory. In a second phase, the FFT engine provides a second portion of the second stream of samples to the second memory, the first memory provides the first portion of the second stream of samples to the CSC, and the CSC responsively generates a third stream of samples.

Abstract: A method for compressing echolocation data is provided. The method includes dividing the echolocation data into a plurality of partitions, and selecting a first partition for processing. The method also includes combining echolocation data from the first partition with echolocation data within a second partition, and combining echolocation data from the first partition with echolocation data within a third partition. The method further includes storing the combined echolocation data for all of the plurality of partitions except for the first partition in a memory.

Abstract: A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B?), and concatenate M2(A) and M2(B?) to obtain an aggregate velocity matrix M2(A&B?). The processor cores perform a second FT on each row of M2(A&B?) to obtain a range and velocity matrix M3(A&B?).

Abstract: A radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. Other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. Processing circuitry performs a Fast Fourier Transform (FFT) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-Doppler array, and performs a FFT on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-Doppler array; identifies peaks in the first and second range-Doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-Doppler arrays to determine a measured phase shift between the two peaks.

Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

Abstract: In some examples, a method includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (LO) frequency of the first device by a target offset and reflected off a target. The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmission frequency and the LO frequency. The method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.

Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.

Abstract: Signal processing comprising, first, determining a plurality of fast Fourier transform (FFT) values corresponding to each sample in a plurality of signal samples, second, variably compressing ones of the FFT values at different non-zero levels of compression, and third, storing the variably compressed ones of the FFT values.

Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.

Abstract: In a radar system, an intermediate frequency amplifier (IFA) is configured with two high-pass filter stages, each having an amplifier and a configurable impedance component. A control signal is activated as the radar system begins to transmit a chirp signal to lower the impedance of the configurable impedance components during an initial portion of the chirp transmission to achieve faster settling of the IFA output signal. After the initial portion, the control signal deactivates while transmission of the chirp continues to increase the impedance of the configurable impedance components to a level sufficient to effectively perform filtering of unwanted signals received by the radar system.

Abstract: An example radar device includes an antenna system, a transmitter having an input, and an output coupled to an input of the antenna system, the transmitter having modulation circuitry to provide frequency modulated continuous wave (FMCW) signals for transmission by the antenna system; a receive signal processing chain; and a digital front-end. The receive signal processing chain includes an input coupled to an output of the antenna system, and is configured to receive radar reflection signals, process the radar reflected signals to generate an intermediate frequency (IF) baseband signal, and digitize the IF baseband signal to generate digital samples of the IF baseband signal. The digital front-end has an input to receive the digital samples of the IF baseband signal and to phase-shift the digital samples in response to a calibration signal.

Abstract: Systems and instruction carrying non-transitory processor-readable mediums are provided to facilitate access of radar data that may be scattered or non-uniformly located within a region of memory for further processing of such radar data. An example system includes counters that increment on different dimensions of the memory region, a lookup table, multipliers, an adder, and a wraparound mechanism to access different sets of non-contiguously stored radar data from a region of memory. The wraparound mechanism performs a wraparound operation when a combined address, generated by the adder based on addresses obtained by the multipliers, is greater than a last valid address in the region. The wraparound operation generates a new combined address that is used to fetch data from the memory. A transform operation is then performed on the fetched data.

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

Abstract: In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.