Abstract: Non-transitory computer-readable mediums and systems are provided in which a portion of each chirp of a series of chirps is held at an offset frequency for a period of time, and in which the offset frequency, the period of time or both is varied or dithered across the chirps of the series of chirps. The portion of a chirp that is held at an offset frequency for a period of time may be a non-active portion of the chirp, during which the chirp is not sampled. In some implementations, the portion of a chirp that is held at an offset frequency for a period of time is during a falling portion of the chirp, which may be at the beginning of the falling portion, or at the end of the falling portion immediately before a rise portion of a succeeding chirp.

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

Abstract: A radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. Other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. Processing circuitry performs a Fast Fourier Transform (FFT) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-Doppler array, and performs a FFT on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-Doppler array; identifies peaks in the first and second range-Doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-Doppler arrays to determine a measured phase shift between the two peaks.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to test RADAR integrated circuits. A radar circuit comprising a local oscillator (LO), a transmitter coupled to the LO and configured to be coupled to a transmission network, a receiver configured to be coupled to the transmission network, and a controller coupled to the LO, the transmitter, and the receiver, the controller to cause the LO to generate a frequency modulated continuous waveform (FMCW), cause the transmitter to modulate the FMCW as a modulated FMCW, cause the transmitter to transmit the modulated FMCW via the transmission network and the receiver to obtain a received FMCW from the transmission network, and in response to obtaining the received FMCW from the receiver, generate a performance characteristic of the radar circuit based on the received FMCW.

Abstract: A non-transitory computer-readable storage device stores machine instructions which, when executed by a processor, cause the processor to determine a chirp period Tc for radar chirps in a radar frame. The chirp period Tc comprises a rising period Trise and a falling period Tfall. The processor determines, for each radar chirp in the radar frame, a corresponding randomized frequency characteristic during Tfall, and causes a radar sensor circuit to generate the radar chirps in the radar frame based on Tc, Trise, Tfall, and the corresponding randomized frequency characteristics. In some implementations, the machine instructions to determine the corresponding randomized frequency characteristic comprise machine instructions to determine a frequency step having a frequency f_step and a period Tstep. At least one of the frequency f_step and the period Tstep is dithered across radar chirps in the radar frame.

Abstract: A radar system is provided and includes a radar transceiver integrated circuit (IC) and a processor coupled to the radar transceiver IC. The radar transceiver IC includes a chirp generator configured to generate a plurality of chirp signals and a phase shifter configured to induce a signal phase shift. The radar transceiver IC is configured to transmit a frame of chirps based on the plurality of chirp signals and generate a plurality of digital signals, each digital signal corresponding to a respective reflection received based on the plurality of chirp signals. The processor is configured to control the phase shifter to induce the signal phase shift in a first subset of chirp signals of the plurality of chirp signals and determine a phase shift induced in the first subset of chirp signals by the phase shifter based on the digital signal.

Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

Abstract: A FMCW radar system with a built-in self-test (BIST) system for monitoring includes a receiver, a transmitter, and a frequency synthesizer. A FMCW chirp timing engine controls timing of operations at least one radar component. The BIST system includes at least one switchable coupling for coupling a first plurality of different analog signals including from a first plurality of selected nodes in the receiver or transmitter that are all coupled to a second number of monitor analog-to-digital converters (ADCs). The second number is less than (<) the first plurality of different analog signals. The BIST system includes a monitor timing engine and controller operating synchronously with the chirp timing engine, that includes a software configurable monitoring architecture for generating control signals including for selecting using the switchable coupling which analog signal to forward to the monitor ADC and when the monitor ADC samples the analog signals.

Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.

Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.

Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar system includes an FMCW signal generator, a number N transmitters, N phase shifters, multiple receivers, and a processor. The FMCW signal generator is configured to generate FMCW chirps. Different ones of the phase shifters have different respective base phase shifts selected in response to N. The transmitter is configured to transmit the phase shifted FMCW chirps. The receivers are configured to receive an FMCW chirp reflected by an object in range of the FMCW radar system. The processor is configured to determine a location of the object in range in response to the received FMCW chirp.

Abstract: A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.

Abstract: A method for a radar system includes transmitting, by a transmit channel of the radar system, a frame comprising first, second, and third chirps. Each chirp has a chirp start frequency, and the chirp start frequency of the transmitted chirps is dithered. The method also includes receiving, by a receive channel of the radar system, a frame of reflected chirps based on the transmitted frame, and generating a digital intermediate frequency (IF) signal.

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Abstract: An example radar device includes an antenna system, a transmitter having an input, and an output coupled to an input of the antenna system, the transmitter having modulation circuitry to provide frequency modulated continuous wave (FMCW) signals for transmission by the antenna system; a receive signal processing chain; and a digital front-end. The receive signal processing chain includes an input coupled to an output of the antenna system, and is configured to receive radar reflection signals, process the radar reflected signals to generate an intermediate frequency (IF) baseband signal, and digitize the IF baseband signal to generate digital samples of the IF baseband signal. The digital front-end has an input to receive the digital samples of the IF baseband signal and to phase-shift the digital samples in response to a calibration signal.

Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

Abstract: A method for calibrating a cascaded radar system includes transmitting first radar transmission signal from a radar device. First radar reflection signals corresponding to the respective first radar transmission signal reflected from calibration target are received at each of the radar devices. The first radar reflection signals are demodulated to generate first baseband signals at each of the radar devices. A second radar transmission signal is modulated with respect to the first radar transmission signal at the respective one of the radar devices. The second radar transmission signal is transmitted from the respective one of the radar devices and are received as second radar reflection signals at each of the radar devices. The second radar reflection signals are demodulated to generate second baseband signals at each of the radar devices, and each of the radar devices are calibrated based on the first and second baseband signals.

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B?), and concatenate M2(A) and M2(B?) to obtain an aggregate velocity matrix M2(A&B?). The processor cores perform a second FT on each row of M2(A&B?) to obtain a range and velocity matrix M3(A&B?).

Abstract: A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.