Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: A semiconductor device, includes: a first inverter that operates on a first supply voltage and includes a transistor with a first polarity and a transistor with a second polarity different from the first polarity; a first inverter array that is connected to a gate of the transistor with the first polarity, includes a predetermined plural number of inverters connected in series, and operates on the first supply voltage; and a second inverter array that is connected to a gate of the transistor with the second polarity and includes inverters of the predetermined plural number connected in series, wherein a first stage inverter in the second inverter array operates on a second supply voltage that is higher than the first supply voltage, and a subsequent stage inverter subsequent to the first stage inverter operates on the first supply voltage.

Abstract: A semiconductor device, includes: a first inverter that operates on a first supply voltage and includes a transistor with a first polarity and a transistor with a second polarity different from the first polarity; a first inverter array that is connected to a gate of the transistor with the first polarity, includes a predetermined plural number of inverters connected in series, and operates on the first supply voltage; and a second inverter array that is connected to a gate of the transistor with the second polarity and includes inverters of the predetermined plural number connected in series, wherein a first stage inverter in the second inverter array operates on a second supply voltage that is higher than the first supply voltage, and a subsequent stage inverter subsequent to the first stage inverter operates on the first supply voltage.

Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: A semiconductor storage device includes a memory array at which writing and reading of plural data are carried out, one pair of write registers that temporarily store write data that is to be written into the memory array, and one pair of read registers that temporarily store read data that is read-out from the memory array.

Abstract: A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

Abstract: A semiconductor storage device includes a memory array at which writing and reading of plural data are carried out, one pair of write registers that temporarily store write data that is to be written into the memory array, and one pair of read registers that temporarily store read data that is read-out from the memory array.

Abstract: A write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.

Abstract: A write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part.

Abstract: A data readout circuit including a 1st PMOS transistor operating in saturation and including a source connected to a power supply, a drain connected to an input terminal a memory cell, and a gate connected to a 1st bias voltage; a 2nd PMOS transistor including a source connected to the drain of the 1st PMOS transistor, a drain connected to an output terminal, and a gate connected to a 2nd bias voltage; a 1st NMOS transistor including a drain connected to the drain of the 2nd PMOS transistor, a source grounded, and a gate connected to a 3rd bias voltage; and a bias voltage section causing the 2nd PMOS transistor to operate in saturation, and supplying the 2nd bias voltage adjusted so as to keep a reference voltage of the input terminal at a junction point between the drain and the source of the 1st and 2nd PMOS transistors respectively.

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line.