Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: A data readout circuit comprises: a 1st PMOS transistor configured to operate in a saturation region and including a source connected to a power supply, a drain connected to an input terminal connected to a memory cell of a data readout object, and a gate to which a 1st bias voltage is supplied; a 2nd PMOS transistor including a source connected to the drain of the 1st PMOS transistor, a drain connected to an output terminal, and a gate to which a 2nd bias voltage is supplied; a 1st NMOS transistor including a drain connected to the drain of the 2nd PMOS transistor, a source grounded, and a gate to which a 3rd bias voltage is supplied; and a bias voltage supply section causing the 2nd PMOS transistor to operate in a saturation region and supplying the 2nd bias voltage to the gate of the 2nd PMOS transistor, wherein the 2nd bias voltage is adjusted so as to keep a reference voltage of the input terminal at a junction point between the drain of the 1st PMOS transistor and the source of the 2nd PMOS transistor.

Abstract: A semiconductor memory cell device includes a first multiplexer selecting a sub-block including a memory cell storing data to be read out in a row, a drain selector selecting a first column line connected to one terminal of the memory cell to be read, a precharge selector selecting a second column line connected to the other terminal of the memory cells adjacent to the one terminal of the memory cell storing the data to be readout, a second multiplexer selecting the sub-block including the second column line, a source selector selecting a third column line connected to the other terminal of the memory cell storing the data to be read out. The second multiplexer and precharge selector, when selecting, apply a first voltage to the second column line, and the source selector, when selecting, applies a second voltage to the third column line.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a step-up booster circuit, a number of pump circuits are connected in series. Pump control signals are outputted from a pump control circuit, and the pump circuits accordingly generate a required raised voltage by stepping up voltages of signals inputted to the respective pump circuits. The step-up circuit includes an activation control circuit which generates a pump activation signal in accordance with provided signals, which direct operation of the step-up circuit. The pump control circuit controls output of the pump control signals in accordance with a voltage of the pump activation signal.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.

Abstract: In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.

Abstract: In a step-up booster circuit, a number of pump circuits are connected in series. Pump control signals CLKA and CLKB are outputted from a pump control circuit, and the pump circuits accordingly generate a required raised voltage VWL by stepping up voltages of signals inputted to the respective pump circuits. The step-up circuit includes an activation control circuit which generates a pump activation signal PMPENN in accordance with signals SAEND and MPMPENN, which direct operation of the step-up circuit. The pump control circuit controls output of the pump control signals CLKA and CLKB in accordance with a voltage of the pump activation signal PMPENN.

Abstract: The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor.

Abstract: A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.

Abstract: A semiconductor device including a first signal path for guiding an input signal from a first pad to an input terminal of a macro cell; a second signal path for guiding a clock from a second pad to a clock input terminal of the macro cell; a third signal path for guiding an output signal from a signal output terminal of the macro cell to a third pad; and a fourth signal path for receiving the clock from the first signal path and guiding the clock to a fourth pad. It is possible to eliminate wiring delay by measuring the time from when the input signal and the clock are supplied by the first and second pads until the output signal is output by the third pad, and the time from when the clock is supplied to the second path until it is output by the fourth pad.

Abstract: The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor.

Abstract: The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor.

Abstract: In order to generate a constant voltage, a reference voltage is generated. Short wave noises are cut off from the reference voltage. A control signal is generated based on the reference voltage and an output voltage. The output voltage is controlled in response to the control signal to provide a constant output voltage.

Abstract: A voltage boosting circuit has two charge pumps connected to an output node from which a boosted potential, higher than the power-supply potential, is supplied to a load circuit. One charge pump is activated when the load circuit is activated, regardless of the output node potential. The other charge pump is activated while the load circuit is active, if the potential of the output node falls below a predetermined level. Use of these two charge pumps reduces electrical noise and ensures that the output node is brought to an adequate potential when the load circuit is activated.

Abstract: A voltage boosting circuit has two charge pumps connected to an output node from which a boosted potential, higher than the power-supply potential, is supplied to a load circuit. One charge pump is activated when the load circuit is activated, regardless of the output node potential. The other charge pump is activated while the load circuit is active, if the potential of the output node falls below a predetermined level. Use of these two charge pumps reduces electrical noise and ensures that the output node is brought to an adequate potential when the load circuit is activated.

Abstract: The semiconductor memory device according to the present invention includes a sense amplifier block sa, a pair of memory cell blocks mc0 and mc1, a pair of word driver blocks wd1-0 and wd1-1, a pair of decoder blocks dec1-0 and dec1-1 and a control circuit block cnt101. Inverters INV0 and INV1 provided at the control circuit block cnt101 respectively invert the potential levels of block selection signals BS0 and BS1, whereas level shifters LS0 and LS1 provided at the control circuit block cnt101 amplify the outputs from the inverters INV0 and INV1 respectively to generate equalize signals EQ0 and EQ1 whose potentials swing back and forth between a second source potential VPP and a ground potential VSS so that high speed access is realized even while energy efficiency and greater capacity are achieved.

Abstract: This semiconductor device comprises: a first signal path for guiding the input signal from a first pad to the input terminal of the macro cell; a second signal path for guiding the clock from a second pad to the clock input terminal of the macro cell; a third signal path for guiding a output signal from the signal output terminal of the macro cell to a third pad; and a forth signal path for receiving the clock from the first signal path and guiding the clock to a fourth pad. It is possible to eliminate the wiring delay by measuring the time from when the input signal and clock are supplied by the first and second pad until the output signal is output by the third pad, and the time from when the clock is supplied to the second path until it is output by the fourth pad.

Abstract: The present invention provides a semiconductor memory capable of achieving redundancy relief for column line failure in a stable manner while realizing greater capacity and higher integration. A column decoder circuit CD11 provided in the semiconductor memory is provided with fuse blocks FB(0)˜FB(127), first decoders DA(0)˜DA(127), redundancy control circuits RL(0)˜RL(127) and RLr, second decoders DB(0)˜DB(255), DBr(0) and DBr(1) and column line drivers DV11(0)˜DV11(255), DV11r(0) and DV11r(1). A redundancy control circuit RL(k) is connected with a column line driver DV11(2k) that drives a column line CL(2k) and a column line driver DV11(2k+1) that drives a column line CL(2k+1) via second decoders DB(2k) and DB2(2k+1) respectively.