Patents by Inventor Katsuhiko Yoshihara
Katsuhiko Yoshihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955440Abstract: A semiconductor device includes an insulating support member, a first and a second conductive layer, a first semiconductor element, a first lead, a first detection conductor and a first gate conductor. The first and second conductive layers are disposed on a front surface of the insulating support member. The first semiconductor includes a first and a second electrode on the same side, and a third electrode disposed on the other side and electrically connected to the first conductive layer. The first lead is connected to the first and second conductive layer. The first detection conductor is connected to the first electrode. The first gate conductor is connected to the second electrode. At least one of the first detection conductor and the first gate conductor has an end connected to the first semiconductor element. The end has a coefficient of linear expansion smaller than that of the first conductive layer.Type: GrantFiled: September 10, 2019Date of Patent: April 9, 2024Assignee: ROHM CO., LTD.Inventor: Katsuhiko Yoshihara
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Publication number: 20240079293Abstract: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Inventors: Katsuhiko YOSHIHARA, Masao SAITO
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Publication number: 20240063164Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.Type: ApplicationFiled: October 27, 2023Publication date: February 22, 2024Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
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Patent number: 11862598Abstract: There is provided a semiconductor device including: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer.Type: GrantFiled: October 6, 2021Date of Patent: January 2, 2024Assignee: ROHM CO., LTD.Inventor: Katsuhiko Yoshihara
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Patent number: 11854937Abstract: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.Type: GrantFiled: December 7, 2020Date of Patent: December 26, 2023Assignee: ROHM CO., LTD.Inventors: Katsuhiko Yoshihara, Masao Saito
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Patent number: 11848295Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.Type: GrantFiled: March 2, 2022Date of Patent: December 19, 2023Assignee: ROHM CO., LTD.Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
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Publication number: 20230077964Abstract: A semiconductor device includes a semiconductor element, a first conductive member, a second conductive member, a connecting member, and a metal plate. The semiconductor element has an element obverse surface and an element reverse surface that are spaced apart from each other in a thickness direction. An obverse surface electrode is provided on the element obverse surface. The first conductive member faces the element reverse surface and is bonded to the semiconductor element. The first conductive member and the second conductive member are spaced apart from each other. The connecting member electrically connects the obverse surface electrode and the second conductive member. The metal plate is interposed between the obverse surface electrode and the connecting member in the thickness direction. The obverse surface electrode and the metal plate are bonded to each other by solid-phase diffusion.Type: ApplicationFiled: February 12, 2021Publication date: March 16, 2023Inventors: Katsuhiko YOSHIHARA, Xiaopeng WU
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Publication number: 20220189904Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.Type: ApplicationFiled: March 2, 2022Publication date: June 16, 2022Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
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Publication number: 20220115351Abstract: There is provided a semiconductor device including: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer.Type: ApplicationFiled: October 6, 2021Publication date: April 14, 2022Inventor: Katsuhiko YOSHIHARA
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Patent number: 11302665Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.Type: GrantFiled: November 6, 2019Date of Patent: April 12, 2022Assignee: ROHM CO., LTD.Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
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Publication number: 20220102264Abstract: A semiconductor device includes: a first wiring layer having a first main surface facing a thickness direction; a second wiring layer having a second main surface facing the same side as the first main surface and located away from the first wiring layer; a first semiconductor element having a first main surface electrode and bonded to the first main surface; a second semiconductor element having a second main surface electrode and bonded to the second main surface; a first terminal electrically connected to the second main surface electrode; a first conductive member bonded to the first main surface electrode and the second main surface; and a second conductive member bonded to the second main surface electrode and the first terminal, wherein the first terminal is located away from the first wiring layer in the thickness direction, and the second conductive member overlaps the first wiring layer in the thickness direction.Type: ApplicationFiled: September 20, 2021Publication date: March 31, 2022Inventor: Katsuhiko YOSHIHARA
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Publication number: 20210407954Abstract: Semiconductor device A1 of the present disclosure includes: semiconductor element 10 (semiconductor elements 10A and 10B) having element obverse face and element reverse face facing toward opposite sides in z direction; support substrate 20 supporting semiconductor element 10; conductive block 60 (first block 61 and second block 62) bonded to element obverse face via first conductive bonding material (block bonding materials 610 and 620); and metal member (lead member 40 and input terminal 32) electrically connected to semiconductor element 10 via conductive block 60. Conductive block 60 has a thermal expansion coefficient smaller than that of metal member. Conductive block 60 and metal member are bonded to each other by a weld portion (weld portions M4 and M2) at which a portion of conductive block 60 and a portion of metal member are welded to each other. Thus, the thermal cycle resistance can be improved.Type: ApplicationFiled: November 8, 2019Publication date: December 30, 2021Inventor: Katsuhiko YOSHIHARA
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Publication number: 20210193592Abstract: A semiconductor device includes an insulating support member, a first and a second conductive layer, a first semiconductor element, a first lead, a first detection conductor and a first gate conductor. The first and second conductive layers are disposed on a front surface of the insulating support member. The first semiconductor includes a first and a second electrode on the same side, and a third electrode disposed on the other side and electrically connected to the first conductive layer. The first lead is connected to the first and second conductive layer. The first detection conductor is connected to the first electrode. The first gate conductor is connected to the second electrode. At least one of the first detection conductor and the first gate conductor has an end connected to the first semiconductor element. The end has a coefficient of linear expansion smaller than that of the first conductive layer.Type: ApplicationFiled: September 10, 2019Publication date: June 24, 2021Inventor: Katsuhiko YOSHIHARA
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Patent number: 11011454Abstract: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device comprising a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.Type: GrantFiled: July 15, 2019Date of Patent: May 18, 2021Assignee: ROHM CO., LTD.Inventors: Katsuhiko Yoshihara, Masao Saito
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Publication number: 20210111099Abstract: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.Type: ApplicationFiled: December 7, 2020Publication date: April 15, 2021Inventors: Katsuhiko YOSHIHARA, Masao SAITO
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Publication number: 20200075529Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Takukazu OTSUKA, Seita IWAHASHI, Maiko HATANO, Ryuta WATANABE, Katsuhiko YOSHIHARA
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Patent number: 10485139Abstract: The power module in which a plurality of switching elements connected in series between a first and second power terminals and a circuit configured to connect connecting points thereof to an output terminal are formed, the power module includes: a heat sink to which the switching elements are contacted; a package configured to seal a perimeter of the plurality of switching elements and a part of each terminal so as to expose at least one portion of the heat sink; and a protruding portion for thickness control configured to regulate a thickness of a thermally-conductive material when contacting the heat sink to the cooling apparatus facing the cooling apparatus via the thermally-conductive material, wherein each terminal is exposed from opposite side surfaces of the package, the opposite side surfaces having a height different from a height of an exposed surface of the cooling apparatus of the package.Type: GrantFiled: January 31, 2018Date of Patent: November 19, 2019Assignee: ROHM CO., LTD.Inventor: Katsuhiko Yoshihara
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Patent number: 10483216Abstract: The power module includes: a ceramics substrate; a source electrode pattern, a drain electrode pattern, a source signal electrode pattern, and a gate signal electrode pattern respectively disposed on the ceramics substrate; a semiconductor device disposed on the drain electrode pattern, the semiconductor device comprising a source pad electrode and a gate pad electrode at a front surface side; a divided leadframe for source bonded to the source electrode pattern and the source pad electrode; and a divided leadframe for gate pad electrode bonded to a gate pad electrode. There is provided a power module having a simplified structure, fabricated through a simplified process, and capable of conducting a large current; and a fabrication method for such a power module.Type: GrantFiled: December 7, 2016Date of Patent: November 19, 2019Assignee: ROHM CO., LTD.Inventor: Katsuhiko Yoshihara
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Publication number: 20190341336Abstract: A power module apparatus (10) comprises: a power module (100A) comprising a package (110) configured to seal a perimeter of a semiconductor device, and a heat radiator (42) bonded to one surface of the package; a cooling device (30) comprising a coolant passage (33) through which coolant water flows, in which the heat radiator is attached to an opening (35) provided on a way of the coolant passage, wherein the heat radiator (42) of the power module (100A) is attached to the opening (35) of the cooling device (30) so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Inventors: Katsuhiko YOSHIHARA, Masao SAITO
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Patent number: 10403561Abstract: A power module apparatus (10) comprises: a power module (100A) comprising a package (110) configured to seal a perimeter of a semiconductor device, and a heat radiator (42) bonded to one surface of the package; a cooling device (30) comprising a coolant passage (33) through which coolant water flows, in which the heat radiator is attached to an opening (35) provided on a way of the coolant passage, wherein the heat radiator (42) of the power module (100A) is attached to the opening (35) of the cooling device (30) so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.Type: GrantFiled: June 4, 2018Date of Patent: September 3, 2019Assignee: ROHM CO., LTD.Inventors: Katsuhiko Yoshihara, Masao Saito