Patents by Inventor Katsuhiro Ishida
Katsuhiro Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10170284Abstract: A plasma processing method according to an aspect includes: preparing a plasma processing apparatus including: a chamber; a lower electrode; an upper electrode; a focus ring surrounding a peripheral edge of the lower electrode; and an annular coil disposed on an upper portion of the upper electrode at a more outer position than the peripheral edge of the lower electrode; placing a substrate on the lower electrode, with a peripheral edge of the substrate surrounded by the focus ring; introducing process gas into the chamber; generating plasma of the process gas by applying high-frequency power across the upper electrode and the lower electrode; and leveling an interface of a plasma sheath on an upper portion of the substrate with that on an upper portion of the focus ring by generating a magnetic field by supplying a current to the annular coil.Type: GrantFiled: September 14, 2016Date of Patent: January 1, 2019Assignees: TOKYO ELECTRON LIMITED, KABUSHIKI KAISHA TOSHIBAInventors: Kenta Yasuda, Toru Kubota, Takashi Kondo, Katsuhiro Ishida
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Publication number: 20170004956Abstract: A plasma processing method according to an aspect includes: preparing a plasma processing apparatus including: a chamber; a lower electrode; an upper electrode; a focus ring surrounding a peripheral edge of the lower electrode; and an annular coil disposed on an upper portion of the upper electrode at a more outer position than the peripheral edge of the lower electrode; placing a substrate on the lower electrode, with a peripheral edge of the substrate surrounded by the focus ring; introducing process gas into the chamber; generating plasma of the process gas by applying high-frequency power across the upper electrode and the lower electrode; and leveling an interface of a plasma sheath on an upper portion of the substrate with that on an upper portion of the focus ring by generating a magnetic field by supplying a current to the annular coil.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Applicants: Tokyo Electron Limited, Kabushiki Kaisha ToshibaInventors: Kenta YASUDA, Toru KUBOTA, Takashi KONDO, Katsuhiro ISHIDA
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Publication number: 20160268294Abstract: A method for forming a pattern in a conductive layer includes forming the conductive layer on an insulating layer, forming an etching mask on the conductive layer, and selectively etching the conductive layer to reach the insulating layer by using the etching mask. The etching mask includes a first portion masking a first area of the conductive layer, a second portion masking a second area that surrounds the first area via at least one opening that defines a boundary between the first portion and the second portion. The etching mask also includes a first communication portion connecting the first portion and the second portion. The at least one opening includes overlapping portions, and the first communication portion is provided between the overlapping portions.Type: ApplicationFiled: August 17, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Junichi HASHIMOTO, Toru MATSUDA, Katsuhiro ISHIDA, Hidetaka NAMBU
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Publication number: 20150379185Abstract: According to one embodiment, there is provided a mask data generation method. The mask data generation method includes obtaining depth information about a pattern depth of a hole included in design information about a semiconductor device. The mask data generation method includes obtaining a first correction rule used to correct, in terms of the pattern depth, a process conversion difference between a resist pattern and a processed pattern. The mask data generation method includes determining temporary mask data including a lithography target pattern by applying a first process conversion difference correction processing to a dimension of hole pattern arranged in design layout data based on the depth information and the first correction rule.Type: ApplicationFiled: September 4, 2014Publication date: December 31, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Tsuyoshi MORISAKI, Satoshi USUI, Katsuhiro ISHIDA
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Publication number: 20130062758Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.Type: ApplicationFiled: March 16, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takashi IMOTO, Yoriyasu Ando, Akira Tanimoto, Masaji Iwamoto, Yasuo Takemoto, Hideo Taguchi, Naoto Takebe, Koichi Miyashita, Jun Tanaka, Katsuhiro Ishida, Shogo Watanabe, Yuichi Sano
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Patent number: 8237295Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.Type: GrantFiled: March 21, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuichi Sano, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
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Patent number: 8231046Abstract: A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire.Type: GrantFiled: September 22, 2009Date of Patent: July 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiro Nakao, Junya Sagara, Katsuhiro Ishida, Noboru Okane
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Publication number: 20110309502Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.Type: ApplicationFiled: March 21, 2011Publication date: December 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yuichi SANO, Takashi Imoto, Naoto Takebe, Katsuhiro Ishida, Tomomi Honda, Yasushi Kumagai
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Patent number: 8039970Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.Type: GrantFiled: January 29, 2008Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Yamamori, Katsuhiro Ishida
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Patent number: 8009123Abstract: In the PDP device, for example, two types of SF lighting patterns (A and B modes) are equally divided and arranged in spatially different regions in a field. For example, the patterns are arranged in a zigzag manner in units of pixels. At all lighting steps, existence of an absence of light-on SF which becomes a cause of false contour is permitted only in one mode. Accordingly, a generation rate of absence of light-on SF per field when the modes are combined is low, and the level of false contour can be reduced. Further, the spatial arrangement of each mode is optionally changed among the fields.Type: GrantFiled: January 25, 2007Date of Patent: August 30, 2011Assignee: Fujitsu Hitachi Plasma Display LimitedInventors: Katsuhiro Ishida, Akira Yamamoto, Ayahito Kojima, Shingo Kubo, Takashi Shiizaki, Hirohito Kuriyama
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Patent number: 7968993Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element.Type: GrantFiled: July 9, 2008Date of Patent: June 28, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Ishida, Ryoji Matsushima
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Patent number: 7855698Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.Type: GrantFiled: August 21, 2006Date of Patent: December 21, 2010Assignee: Hitachi LimitedInventors: Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka, Masaya Tajima, Katsuhiro Ishida, Kiyotaka Ogawa, Toshio Ueda
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Publication number: 20100255637Abstract: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro ISHIDA, Ryoji Matsushima
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Patent number: 7795667Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.Type: GrantFiled: July 3, 2003Date of Patent: September 14, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Iguchi, Katsuhiro Ishida, Hiroaki Tsunoda, Hirohisa Iizuka, Hiroaki Hazama, Seiichi Mori
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Publication number: 20100181367Abstract: A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wireType: ApplicationFiled: September 22, 2009Publication date: July 22, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiro Nakao, Junya Sagara, Katsuhiro Ishida, Noboru Okane
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Patent number: 7755175Abstract: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.Type: GrantFiled: November 2, 2006Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Ishida, Ryoji Matsushima
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Patent number: 7719117Abstract: A semiconductor device includes a semiconductor substrate, a lower wiring layer formed on the semiconductor substrate, a first interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.Type: GrantFiled: July 26, 2007Date of Patent: May 18, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Ishida, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
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Publication number: 20100009513Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a gate electrode film on the gate insulating film, and forming a plurality of trenches by etching the gate electrode film, the gate insulating film and the semiconductor substrate so that an upper portion of the gate electrode film includes a tapered side surface and a lower portion of the gate electrode film includes a side surface perpendicular to a surface of the semiconductor substrate. The method also includes forming an element isolation insulating film in the trenches, including forming a deposition type insulating film in the trenches and forming a coating type insulating film on the deposition type insulating film, and removing the element isolation insulating film by a dry etching method so that the tapered side surfaced of the gate electrode film is exposed and the perpendicular side surface of the gate electrode film is covered by the element isolation insulating film.Type: ApplicationFiled: September 21, 2009Publication date: January 14, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuhiro Ishida
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Publication number: 20090040206Abstract: A driving method of a plasma display panel which performs image display using a plurality of sub-fields. In a sustain discharge period, a first sustain discharge waveform and a second sustain discharge waveform are applied, the second sustain discharge waveform having a timing of voltage clamping at a rising edge of a pulse which is earlier than that of the first sustain discharge waveform. In a predetermined sub-field in one frame, the first sustain discharge waveform is repeatedly applied without applying the second sustain discharge waveform, and in other sub-fields, the first sustain discharge waveform and the second sustain discharge waveform are repeatedly applied.Type: ApplicationFiled: October 2, 2008Publication date: February 12, 2009Inventors: Takashi Shiizaki, Katsuhiro Ishida
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Publication number: 20090014894Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element.Type: ApplicationFiled: July 9, 2008Publication date: January 15, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro Ishida, Ryoji Matsushima