Patents by Inventor Katsuhiro Ishida
Katsuhiro Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080179757Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.Type: ApplicationFiled: January 29, 2008Publication date: July 31, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro YAMAMORI, Katsuhiro Ishida
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Publication number: 20080099532Abstract: A wire bonding apparatus comprising: a capillary configured to have inserted therethrough a wire; a damper provided above the capillary and able to clamp hold the wire; and a load sensor configured to measure load incurred on the wire.Type: ApplicationFiled: October 4, 2007Publication date: May 1, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiro Nakao, Junya Sagara, Katsuhiro Ishida, Noboru Okane
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Publication number: 20080055288Abstract: A flat display apparatus comprises a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other, and has a characteristic such that as the amount of driving load of the flat display panel increases, the activation energy of discharge gas increases and the panel driving voltage decreases. In a driving method for the flat display apparatus, when the amount of driving load of the flat display panel increases (S1 to S4), the driving voltage of the scanning electrode or the driving voltage (Vd) of the address electrode is reduced.Type: ApplicationFiled: April 11, 2005Publication date: March 6, 2008Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITEDInventors: Toyoshi Kawada, Katsuhiro Ishida, Yuji Sano, Yoshinori Okada
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Publication number: 20080048942Abstract: In the PDP device, for example, two types of SF lighting patterns (A and B modes) are equally divided and arranged in spatially different regions in a field. For example, the patterns are arranged in a zigzag manner in units of pixels. At all lighting steps, existence of an absence of light-on SF which becomes a cause of false contour is permitted only in one mode. Accordingly, a generation rate of absence of light-on SF per field when the modes are combined is low, and the level of false contour can be reduced. Further, the spatial arrangement of each mode is optionally changed among the fields.Type: ApplicationFiled: January 25, 2007Publication date: February 28, 2008Inventors: Katsuhiro Ishida, Akira Yamamoto, Ayahito Kojima, Shingo Kubo, Takashi Shiizaki, Hirohito Kuriyama
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Publication number: 20080036089Abstract: A semiconductor device includes a semiconductor substrate, and an interlayer wiring structure further including a lower wiring layer formed on the semiconductor substrate, a first interlayer an interlayer wiring layer including an interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.Type: ApplicationFiled: July 26, 2007Publication date: February 14, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro ISHIDA, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
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Patent number: 7268069Abstract: A method of fabricating a semiconductor device includes forming a lower wiring layer on a semiconductor substrate, forming an interlayer insulating film on the lower wiring layer, layer, forming a plurality of. contact plugs in the interlayer insulating film so that the contact plugs are brought into electrical contact with the lower wiring layer, thereby forming an interlayer wiring layer, forming an upper wiring, layer on the interlayer wiring layer so that the upper wiring layer is brought into electrical contact with the contact plugs, and patterning the upper wiring layer so that the upper wiring layer corresponds to the contact plugs. In the patterning, after the upper wiring layer has been etched, the exposed interlayer insulating film and the exposed contact plugs are etched.Type: GrantFiled: November 16, 2004Date of Patent: September 11, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiro Ishida, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
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Patent number: 7245076Abstract: A structure, in which the frame can be successfully fixed to the plasma display apparatus at a low cost, has been disclosed. The plasma display apparatus comprises a plasma display panel, circuit substrates having drive circuits to drive the plasma display panel, a main frame to mount the circuit substrates, and adhesive tapes to fix the plasma display panel to the main frame, and small holes are provided on the portion to which the adhesive tapes of the main frame are fixed so that they are arranged regularly at established intervals. When the adhesive tapes and the main frame are fixed, no air bubbles form between the adhesive tapes and the main frame because plural small holes are provided on the portion to which the adhesive tapes of the main frames are fixed.Type: GrantFiled: November 29, 2001Date of Patent: July 17, 2007Assignee: Fujitsu Hitachi Plasma Display LimitedInventors: Hideki Isohata, Katsuhiro Ishida, Hideo Kimura
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Publication number: 20070102801Abstract: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.Type: ApplicationFiled: November 2, 2006Publication date: May 10, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro Ishida, Ryoji Matsushima
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Publication number: 20070046574Abstract: A plasma display device capable of suppressing the streaking without losing the luminance in an AC plasma display device is provided. In an AC plasma display device in which one screen is comprised of a plurality of sub-fields, and an image is displayed by generating sustain discharges several times between display electrodes in each sub-field, periods where the sustain discharge is generated several times in each sub-field include a plurality of sustain discharge periods with different single sustain discharge currents, for example, a sustain discharge period with small single sustain discharge current and a sustain discharge period with large single sustain discharge current, and a driving circuit, which increases a ratio of the number of sustain discharges in the sustain discharge period with large single sustain discharge current relative to that in the sustain discharge period with small single sustain discharge current, is provided.Type: ApplicationFiled: August 30, 2006Publication date: March 1, 2007Inventors: Takashi Shizaki, Katsuhiro Ishida
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Publication number: 20060279482Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.Type: ApplicationFiled: August 21, 2006Publication date: December 14, 2006Applicant: HITACHI, LTDInventors: Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka, Masaya Tajima, Katsuhiro Ishida, Kiyotaka Ogawa, Toshio Ueda
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Publication number: 20060237754Abstract: A semiconductor device includes a semiconductor substrate having a plurality of trenches, a plurality of element isolation regions formed by burying an element isolation insulating film in the trenches, a gate insulating film formed in an element formation region defined between the element isolation regions on the semiconductor substrate, and a gate electrode including a lower gate part which is formed on the gate insulating film in the element formation region and has a side interposed between upper sidewalls of the element isolation region. The gate electrode further includes an upper gate part which is located over the lower gate part and has an underside in contact with the lower gate part. The upper gate part is tapered so that its width is decreased upward from a side end of the underside thereof.Type: ApplicationFiled: April 21, 2006Publication date: October 26, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Katsuhiro Ishida
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Patent number: 7119766Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.Type: GrantFiled: May 17, 2004Date of Patent: October 10, 2006Assignee: Hitachi, Ltd.Inventors: Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka, Masaya Tajima, Katsuhiro Ishida
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Publication number: 20060214887Abstract: Conventionally, in an image display apparatus for gray-scale representation with two fields by a multiple gray-scaling scheme in which selective On-states in an odd field and an even field are made to differ, there has been a problem of deterioration in image quality due to occurrence of motion noise and flicker, for example. An image display method, in which a picture of one frame is configured by a plurality of sub-fields with different light-emitting display luminance levels, different selective On-states are capable of making to differ in accordance with display date inputted to an odd field and an even field, and a dither pattern for adding an arbitrary amount of data is capable of being inserted in accordance with the inputted display data, comprises the step of, for sorting the selective On-states in the odd and even fields and sorting the dither pattern, making at least one of a horizontal direction and a vertical direction to differ.Type: ApplicationFiled: March 24, 2006Publication date: September 28, 2006Inventors: Katsuhiro Ishida, Takashi Shiizaki, Akira Yamamoto, Shigeharu Asao
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Publication number: 20060214884Abstract: In a conventional plasma display panel driving method, all sub-frames each require a driving sequence for resetting a charge, thereby increasing a background light-emission intensity and reducing contrast. A plasma display panel driving method according to the present invention comprises the steps of: configuring one frame by a plurality of sub-frames, and setting, for each of the sub-frames, an address period for using every other one of the display electrodes as a scan electrode to cause the address discharge to occur by the scan electrode and the address electrode, and a display period for causing a surface discharge to occur between the display electrodes; and in at least two sub-frames of the plurality of sub-frames configuring one frame, causing a discharge to occur in only one of two display lines sharing one scan electrode in the address period and the display period.Type: ApplicationFiled: March 23, 2006Publication date: September 28, 2006Inventors: Takashi Shiizaki, Katsuhiro Ishida
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Patent number: 7095390Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.Type: GrantFiled: April 12, 2000Date of Patent: August 22, 2006Assignee: Fujitsu LimitedInventors: Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka, Masaya Tajima, Katsuhiro Ishida
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Publication number: 20050167843Abstract: A semiconductor device includes a semiconductor substrate and an interlayer wiring structure further including a lower wiring layer formed on the semiconductor substrate, an interlayer wiring layer including an interlayer insulating film formed on the lower wiring layer and a plurality of contact plugs each formed so as to extend through the interlayer insulating film to be brought into electrical contact with the lower wiring layer, an upper wiring layer patterned so as to be in electrical contact with upper faces of the contact plugs, and a recessed portion formed by recessing the interlayer insulating film and the contact plugs exposed in the interlayer wiring layer with respect to at least a portion with a short distance between wirings so as to correspond to a shape of the upper wiring layer.Type: ApplicationFiled: November 16, 2004Publication date: August 4, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro Ishida, Hiroshi Sugiura, Makoto Hasegawa, Katsuya Ito
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Publication number: 20050167745Abstract: A semiconductor device includes a semiconductor substrate having an upper face, a plurality of trenches formed in the semiconductor substrate, an element isolating film embedded in each trench and having a top located higher than the upper face of the semiconductor substrate, a gate insulating film formed on the semiconductor substrate so as to be located between the element isolating films adjacent to each other, and a gate electrode formed on the gate insulating film and having a top located higher than the top of the element isolating film. The element isolating film has a recess formed on the top thereof so that the recess extends toward the semiconductor substrate.Type: ApplicationFiled: November 22, 2004Publication date: August 4, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiro Ishida, Katsuya Ito
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Publication number: 20040263434Abstract: A display driving method drives a display to make a gradation display on a screen of the display depending on a length of a light emission time in each of sub fields forming 1 field, where 1 field is a time in which an image is displayed, N sub fields SF1 through SFN form 1 field, and each sub field includes an address display-time in which a wall charge is formed with respect to all pixels which are to emit light within the sub field and a sustain time which is equal to the light emission time and determines a luminance level. The display driving method includes the steps of setting the sustain times of each of the sub fields approximately constant within 1 field, and displaying image data on the display using N+1 gradation levels from a luminance level 0 to a luminance level N.Type: ApplicationFiled: May 17, 2004Publication date: December 30, 2004Applicant: FUJITSU LIMITEDInventors: Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka, Masaya Tajima, Katsuhiro Ishida, Kiyotaka Ogawa, Toshio Ueda
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Publication number: 20040099900Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.Type: ApplicationFiled: July 3, 2003Publication date: May 27, 2004Inventors: Tadashi Iguchi, Katsuhiro Ishida, Hiroaki Tsunoda, Hirohisa Iizuka, Hiroaki Hazama, Seiichi Mori
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Patent number: 6724356Abstract: In a PDP unit, a display frame for one screen comprises a plurality of sub-frames, the luminance of each of which is determined by a sustaining pulse number. A length of one frame is calculated from the length of one cycle of a vertical synchronization signal and a sub-frame condition determination circuit determines, from the length of one frame, the number of sub-frames, the luminance of each sub-frame and a total sustaining pulse number. A load factor is calculated from an external input signal. A further circuit determines a maximum display luminance from consumed power and calculates a luminance factor, and yet a further circuit corrects the luminance drop due to a load from the total sustaining pulse number, the luminance ratio and the load factor for the respective sub-frame and calculates sustaining pulse numbers for the respective sub-frames.Type: GrantFiled: March 30, 2000Date of Patent: April 20, 2004Assignee: Fujitsu LimitedInventors: Ayahito Kojima, Hiroyuki Wakayama, Hirohito Kuriyama, Katsuhiro Ishida, Akira Yamamoto