Patents by Inventor Katsuhiro Kitagawa
Katsuhiro Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901036Abstract: Apparatuses for controlling power supply to sense amplifiers are described. An example apparatus includes a bank. The bank includes: a first plurality of memory cells; a second plurality of memory cells; first sense amplifiers coupled to the first plurality of memory cells; second sense amplifiers coupled to the second plurality of memory cells; a first power control circuit and a coupled to the first sense amplifiers at a common power supply node; and a second power control circuit coupled to the second sense amplifiers at the common power supply node. The first and second power control circuits receive a plurality of control signals. The first and second power control circuits comprise first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals. The first drive strength and the second drive strength are different from each other.Type: GrantFiled: March 10, 2022Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventor: Katsuhiro Kitagawa
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Publication number: 20230290386Abstract: Apparatuses for controlling power supply to sense amplifiers are described. An example apparatus includes a bank. The bank includes: a first plurality of memory cells; a second plurality of memory cells; first sense amplifiers coupled to the first plurality of memory cells; second sense amplifiers coupled to the second plurality of memory cells; a first power control circuit and a coupled to the first sense amplifiers at a common power supply node; and a second power control circuit coupled to the second sense amplifiers at the common power supply node. The first and second power control circuits receive a plurality of control signals. The first and second power control circuits comprise first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals. The first drive strength and the second drive strength are different from each other.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Applicant: MICRON TECHNOLOGY, INC.Inventor: Katsuhiro Kitagawa
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Patent number: 11651815Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.Type: GrantFiled: February 1, 2022Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
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Patent number: 11605421Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.Type: GrantFiled: July 17, 2020Date of Patent: March 14, 2023Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Toru Ishikawa, Minari Arai, Nobuki Takahashi
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Patent number: 11462259Abstract: Apparatuses and methods for controlling internal current are disclosed herein, An example apparatus includes a semiconductor device including a power node. The semiconductor device receives power as an internal current, and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current and provides a second portion of the internal current as an external current at the power node during the first mode. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.Type: GrantFiled: December 7, 2020Date of Patent: October 4, 2022Assignee: Micron Technology, Inc.Inventor: Katsuhiro Kitagawa
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Publication number: 20220180914Abstract: Apparatuses and methods for controlling internal current are disclosed herein, An example apparatus includes a semiconductor device including a power node. The semiconductor device receives power as an internal current, and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current and provides a second portion of the internal current as an external current at the power node during the first mode. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.Type: ApplicationFiled: December 7, 2020Publication date: June 9, 2022Applicant: Micron Technology, Inc.Inventor: Katsuhiro Kitagawa
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Publication number: 20220157367Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
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Patent number: 11270758Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.Type: GrantFiled: July 29, 2020Date of Patent: March 8, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
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Publication number: 20220036939Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
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Publication number: 20220020422Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.Type: ApplicationFiled: July 17, 2020Publication date: January 20, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Katsuhiro Kitagawa, Toru Ishikawa, Minari Arai, Nobuki Takahashi
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Patent number: 10937473Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.Type: GrantFiled: August 8, 2018Date of Patent: March 2, 2021Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Akira Yamashita
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Patent number: 10840910Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.Type: GrantFiled: November 1, 2018Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventor: Katsuhiro Kitagawa
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Patent number: 10803923Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: GrantFiled: June 18, 2019Date of Patent: October 13, 2020Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
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Patent number: 10734046Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.Type: GrantFiled: June 10, 2019Date of Patent: August 4, 2020Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
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Publication number: 20200118608Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.Type: ApplicationFiled: June 10, 2019Publication date: April 16, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
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Publication number: 20200051603Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.Type: ApplicationFiled: August 8, 2018Publication date: February 13, 2020Inventors: Katsuhiro Kitagawa, Akira Yamashita
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Publication number: 20190304532Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Applicant: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
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Patent number: 10418081Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.Type: GrantFiled: October 10, 2018Date of Patent: September 17, 2019Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
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Patent number: 10339998Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: GrantFiled: March 27, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
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Publication number: 20190074838Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.Type: ApplicationFiled: November 1, 2018Publication date: March 7, 2019Applicant: Micron Technology, Inc.Inventor: Katsuhiro Kitagawa