Patents by Inventor Katsuhiro Kitagawa

Katsuhiro Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220180914
    Abstract: Apparatuses and methods for controlling internal current are disclosed herein, An example apparatus includes a semiconductor device including a power node. The semiconductor device receives power as an internal current, and further operates in a first mode and a second mode. The semiconductor device consumes more power in the second mode than in the first mode. The semiconductor device consumes a first portion of the internal current and provides a second portion of the internal current as an external current at the power node during the first mode. The semiconductor device consumes a third portion of the internal current that is greater than the first portion of the internal current during the second mode.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Publication number: 20220157367
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Patent number: 11270758
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 8, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Publication number: 20220036939
    Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Yoshihito Morishita, Daigo Toyama, Takamasa Suzuki
  • Publication number: 20220020422
    Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Toru Ishikawa, Minari Arai, Nobuki Takahashi
  • Patent number: 10937473
    Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita
  • Patent number: 10840910
    Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 10803923
    Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
  • Patent number: 10734046
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
  • Publication number: 20200118608
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Application
    Filed: June 10, 2019
    Publication date: April 16, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
  • Publication number: 20200051603
    Abstract: Drivers for read and write operations of memory arrays are described. In one aspect, a memory device can include an input/output (I/O) circuit to facilitate read and write operations with the memory device. One driver can generate clock signals for the command circuit to aid with the performance of the write operations. Another driver can generate clock signals for the I/O circuit to aid with the performance of the read operations.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Katsuhiro Kitagawa, Akira Yamashita
  • Publication number: 20190304532
    Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
  • Patent number: 10418081
    Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Akira Yamashita, Shuichi Murai, Kohei Nakamura
  • Patent number: 10339998
    Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
  • Publication number: 20190074838
    Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.
    Type: Application
    Filed: November 1, 2018
    Publication date: March 7, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 10218342
    Abstract: Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: February 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 10140275
    Abstract: Disclosed is a non-transitory computer-readable recording medium having stored therein a message information generating program, which when processed by one or more processors, causes a computer to execute a process. The process includes acquiring first information having both a character string input by handwriting and a character color related to the character string input by the handwriting, specifying a form of the character string based on the acquired first information, specifying an address associated with the specified form by referring to a storage configured to store an address of a message destination in association with a form of a character string, and generating message information with the specified address as a destination, the message information including second information corresponding to the character string.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 27, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Katsuhiro Kitagawa
  • Patent number: 10128847
    Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa
  • Publication number: 20170302256
    Abstract: Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal, and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: KATSUHIRO KITAGAWA
  • Publication number: 20170250689
    Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.
    Type: Application
    Filed: February 26, 2016
    Publication date: August 31, 2017
    Applicant: Micron Technology, Inc.
    Inventor: Katsuhiro Kitagawa