Patents by Inventor Katsuhiro Kitagawa
Katsuhiro Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140177361Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.Type: ApplicationFiled: February 28, 2014Publication date: June 26, 2014Inventor: Katsuhiro KITAGAWA
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Patent number: 8760205Abstract: A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level.Type: GrantFiled: March 11, 2013Date of Patent: June 24, 2014Inventors: Katsuhiro Kitagawa, Shotaro Kobayashi
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Publication number: 20140167826Abstract: Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output, an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.Type: ApplicationFiled: February 24, 2014Publication date: June 19, 2014Inventor: Katsuhiro KITAGAWA
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Patent number: 8713331Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.Type: GrantFiled: March 15, 2010Date of Patent: April 29, 2014Inventor: Katsuhiro Kitagawa
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Patent number: 8698535Abstract: Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.Type: GrantFiled: August 14, 2012Date of Patent: April 15, 2014Inventor: Katsuhiro Kitagawa
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Publication number: 20140035639Abstract: Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.Type: ApplicationFiled: August 5, 2013Publication date: February 6, 2014Applicant: Elpida Memory, Inc.Inventors: Katsuhiro KITAGAWA, Hiroki TAKAHASHI
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Publication number: 20130249613Abstract: A semiconductor device according to the present invention includes an input circuit that is connected between an input node and an output node and that changes a level of the output node corresponding to a signal supplied to the input node, wherein when a control signal represents a first mode, a speed at which input circuit changes the level of the output node from a first level to a second level is greater than the speed at which input circuit changes the level of the output node from the second level to the first level and when the control signal represents a second mode, the speed at which input circuit changes the level of the output node from the second level to the first level is greater than the speed at which the input circuit changes the level of the output node from the first level to the second level.Type: ApplicationFiled: March 11, 2013Publication date: September 26, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Katsuhiro KITAGAWA, Shotara KOBAYASHI
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Patent number: 8436657Abstract: To provide an output driver that outputs read data to outside and a mode register that sets a swing capability of the output driver. A transition start timing of the read data driven by the output driver is made relatively earlier when a swing capability of the output driver set by the mode register is set to be relatively large, and the transition start timing is relatively delayed when the swing capability of the output driver set by the mode register is set to be relatively small. With this configuration, a timing when the read data exceeds a threshold level can be caused to coincide with a desired timing regardless of the swing capability of the output driver.Type: GrantFiled: February 19, 2010Date of Patent: May 7, 2013Assignee: Elpida Memory, Inc.Inventor: Katsuhiro Kitagawa
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Publication number: 20130043919Abstract: Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.Type: ApplicationFiled: August 14, 2012Publication date: February 21, 2013Inventor: Katsuhiro KITAGAWA
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Patent number: 8299829Abstract: To provide a DLL circuit incorporating a duty adjustment circuit that is independent of the frequency of a clock signal. The DLL circuit includes: a delay line that delays a first internal clock signal to generate a second internal clock signal; a counter circuit that specifies an amount of delay of the delay line; a counter control circuit that adjusts a count value of the counter circuit; and a subtraction circuit that determines a difference between first and second count values at which the rise edge of the first internal clock signal coincides with that of a replica clock signal. The fall edge of the second internal clock signal is adjusted based on a value equivalent to one-half of the difference obtained. This prevents the applicable frequency range from being limited as with a type of duty adjustment circuit that alternately discharges capacitors.Type: GrantFiled: March 11, 2011Date of Patent: October 30, 2012Assignee: Elpida Memory, Inc.Inventor: Katsuhiro Kitagawa
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Publication number: 20120044776Abstract: A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in an active state, in which a data signal can be received, while the control signal is in an active state, and otherwise controlled to be in an inactive state.Type: ApplicationFiled: August 19, 2011Publication date: February 23, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Katsuhiro KITAGAWA, Shotaro KOBAYASHI
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Publication number: 20110227619Abstract: To provide a DLL circuit incorporating a duty adjustment circuit that is independent of the frequency of a clock signal. The DLL circuit includes: a delay line that delays a first internal clock signal to generate a second internal clock signal; a counter circuit that specifies an amount of delay of the delay line; a counter control circuit that adjusts a count value of the counter circuit; and a subtraction circuit that determines a difference between first and second count values at which the rise edge of the first internal clock signal coincides with that of a replica clock signal. The fall edge of the second internal clock signal is adjusted based on a value equivalent to one-half of the difference obtained. This prevents the applicable frequency range from being limited as with a type of duty adjustment circuit that alternately discharges capacitors.Type: ApplicationFiled: March 11, 2011Publication date: September 22, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Katsuhiro Kitagawa
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Publication number: 20110169527Abstract: To provide an output driver that outputs read data to outside and a mode register that sets a swing capability of the output driver. A transition start timing of the read data driven by the output driver is made relatively earlier when a swing capability of the output driver set by the mode register is set to be relatively large, and the transition start timing is relatively delayed when the swing capability of the output driver set by the mode register is set to be relatively small. With this configuration, a timing when the read data exceeds a threshold level can be caused to coincide with a desired timing regardless of the swing capability of the output driver.Type: ApplicationFiled: February 19, 2010Publication date: July 14, 2011Applicant: ELPIDA MEMORY INC.Inventor: KATSUHIRO KITAGAWA
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Patent number: 7932759Abstract: A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.Type: GrantFiled: September 4, 2009Date of Patent: April 26, 2011Assignee: Elpida Memory, Inc.Inventors: Tsuneo Abe, Katsuhiro Kitagawa
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Publication number: 20110022808Abstract: An output driver has a first driver connected between a first power source and an output terminal and a second driver connected between a second power source and the output terminal. One of the first driver and the second driver has two driving parts connected in parallel to each other. The two driving parts and the other of the first driver and the second driver are operated by independent input signals.Type: ApplicationFiled: July 14, 2010Publication date: January 27, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Katsuhiro KITAGAWA, Hiroshi ICHIKAWA
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Patent number: 7876138Abstract: A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.Type: GrantFiled: December 1, 2008Date of Patent: January 25, 2011Assignee: Elpida Memory, Inc.Inventors: Shotaro Kobayashi, Katsuhiro Kitagawa
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Publication number: 20100231275Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.Type: ApplicationFiled: March 15, 2010Publication date: September 16, 2010Applicant: Elpida Memory, Inc.Inventor: Katsuhiro KITAGAWA
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Publication number: 20100123495Abstract: A DLL circuit includes a delay line that generates an internal clock signal by delaying an external clock signal CLK, a counter circuit that sets a delay amount of the delay line, a phase detecting circuit that generates a phase determination signal based on a phase of the external clock signal, and an antialiasing circuit that prohibits the counter circuit to update a count value based on the phase determination signal, in response to a fact that a jitter component included in the external clock signal is equal to or higher than a predetermined frequency. With this configuration, a problem that the internal clock signal is continuously controlled to a wrong direction due to malfunction of aliasing does not occur.Type: ApplicationFiled: December 1, 2008Publication date: May 20, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Shotaro Kobayashi, Katsuhiro Kitagawa
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Publication number: 20100060334Abstract: A DLL includes a first variable delay circuit that variably delays a first transition of an external signal, a second variable delay circuit that variably delays a second transition of the external signal, a synthesis circuit that synthesizes output signals of the first variable delay circuit and the second variable delay circuit, a duty change detection circuit that changes and detects the duty of an output signal of the synthesis circuit, and delay control circuits that vary the delay of the first variable delay circuit or the second variable delay circuit in accordance with the result of duty detection by the duty change detection circuit.Type: ApplicationFiled: September 4, 2009Publication date: March 11, 2010Applicant: Elpida Memory, IncInventors: Tsuneo Abe, Katsuhiro Kitagawa