Abstract: An MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) of the present invention comprises two source.multidot.drain impurity regions formed spaced apart from each other in a semiconductor substrate. At least a drain side of the two impurity regions has a so called LDD structure in which a region of higher concentration and a region of lower concentration are off set. A gate electrode having a rectangular cross section is formed on the semiconductor substrate between the source and drain with an insulating film interposed therebetween. The gate electrode fully covers the lower concentration region of the LDD structure directly therebelow. The position of the side surface of the gate electrode is approximately aligned with the end surface of the region of higher concentration. The impurity region of lower concentration of the LDD is formed by oblique ion implantation.

Abstract: A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal.

Abstract: A method for preparing a MISFET of a minute size with the channel length of not more than 2 .mu.m between a source and a drain, comprises the steps of forming a mask for exposing a region for forming a well on a planar surface of a semiconductor substrate, and introducing ions at a predetermined energy into the well region by using the mask. The predetermined energy is such as to form a peak of the impurity concentration distribution at a position deeper than the bottom surface of the source and the drain and to maintain the layer of at least a partial layer of the channel at an impurity concentration lower than 10 .sup.16 cm.sup.-3 so that a high speed carrier movement in the channel is provided without causing a punch-through phenomenon.

Abstract: A micro MIS type FET comprises first conductivity type source/drain regions formed in a surface of a semiconductor layer mutually spaced apart by a distance of less than 2 .mu.m, a second conductivity type channel layer having an impurity concentration of less than 1.times.10.sup.16 /cm.sup.3 formed between the source/drain regions to have a depth less than depths of the source/drain regions, and a second conductivity type threshold voltage control region having an impurity concentration of more than 1.times.10.sup.17 /cm.sup.3 beneath the channel layer.

Abstract: A method and apparatus for manufacturing a semiconductor device having a thin layer of material formed on a semiconductor substrate with a much improved interface between them are disclosed. A silicon substrate is heated up to a temperature around 300.degree. C. in the presence of ozone gas under exposure to UV light. Through this process, organic contaminants that might be present on the surface of the silicon substrate are dissipated by oxidation, and a thin oxide film is formed on the substrate surface on the other. The silicon substrate with the thin oxide film coated thereon is then heated up to temperatures of 200.degree.-700.degree. C. in the presence of HCl gas under illumination to UV light to strip the oxide film off the substrate surface, thereby exposing the cleaned substrate surface. Finally, HCl cleaned surface of the silicon substrate is coated with a thin layer of material such as monocrystalline silicon without exposing the cleaned substrate surface.

Abstract: A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface.

Abstract: A method of forming a well on a semiconductor substrate and a transistor on the main surface of this well. A mask exposing a region for the well is formed on the main surface of the semiconductor substrate. Subsequently, ions of impurities for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using this mask with high energy giving concentration distribution of impurities which becomes maximum at a place deeper than a region for a transistor. Subsequently, ions of impurities of the same conductivity type as that of ions for forming the well are implanted on the main surface of the region for the well of the semiconductor substrate using the mask with low energy giving concentration distribution of impurities in which impurities stay in the region for the channel of the transistor.

Abstract: A complementary field effect element develops an intensified latch-up preventive property even if the distance between the emitters of parasitic transistors is short, and a method of producing the same are disclosed. The complementary field effect element includes a high concentration impurity layer (16) formed by ion implantation in the boundary region between a P-well (2) and an N-well (3) which are formed adjacent each other on the main surface of a semiconductor substrate (1). Therefore, carriers passing through the boundary region between the P-well (2) and the N-well (3) are decreased, so that even if the distance between the emitters (4, 5) of parasitic transistors is short, there is obtained an intensified latch-up preventive property.

Abstract: A semiconductor device comprises a P-type semiconductor substrate having a major surface, an insulating film formed on the major surface of the semiconductor substrate, a first polycrystalline silicon layer formed on the insulating film, an n.sup.+ diffused layer formed on the substrate and adjacent to an end portion of the first polycrystalline silicon layer, and a side wall formed on the end portion of the first polycrystalline silicon layer and formed of a second polycrystalline silicon layer for connecting the end portion of the first polycrystalline silicon layer with the n.sup.+ diffused layer.

Abstract: An MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) of the present invention comprises two source.multidot.drain impurity regions formed spaced apart from each other in a semiconductor substrate. At least a drain side of the two impurity regions has a so called LDD structure in which a region of higher concentration and a region of lower concentration are off set. A gate electrode having a rectangular cross section is formed on the semiconductor substrate between the source and drain with an insulating film interposed therebetween. The gate electrode fully covers the lower concentration region of the LDD structure directly therebelow. The position of the side surface of the gate electrode is approximately aligned with the end surface of the region of higher concentration. The impurity region of lower concentration of the LDD is formed by oblique ion implantation.

Abstract: A method of manufacturing a semiconductor memory device having a peripheral circuit portion, the operating voltage of which is relatively high and a memory array portion, the operating voltage of which is relatively low comprises the steps of forming an inversion preventing layer on the peripheral circuit portion, forming an oxide layer for isolation between devices adjacent thereto, forming on the memory array portion the inversion preventing layer, the impurity concentration of which is higher than that of the peripheral circuit portion and forming the oxide layer on the peripheral circuit portion at the same time that the oxide layer for isolation between devices is formed adjacent thereto.

Abstract: A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.

Abstract: A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode.

Abstract: A method and apparatus for manufacturing a semiconductor device having a thin layer of material formed on a semiconductor substrate with a much improved interface between them are disclosed. A silicon substrate is heated up to a temperature around 300.degree. C. in the presence of ozone gas under exposure to UV light. Through this process, organic contaminants that might be present on the surface of the silicon substrate are dissipated by oxidation, and a thin oxide film is formed on the substrate surface on the other. The silicon substrate with the thin oxide film coated thereon is then heated up to temperature of 200.degree.-700.degree. C. in the presence of HCl gas under illumination to UV light to strip the oxide film off the substrate surface, thereby exposing the cleaned substrate surface. Finally, HCl cleaned surface of the silicon substrate is coated with a thin layer of material such as monocrystalline silicon without exposing the cleaned substrate surface.

Abstract: A semiconductor memory device comprises a p.sup.- -type semiconductor substrate (1), thin p.sup.+ -type regions (15, 80) formed thereon, n.sup.+ -type regions (6, 7) surrounded with the p.sup.+ -type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n.sup.+ -type region (6), and a second gate electrode (3) formed on the p.sup.+ -type region (80) and serving as a word line. The p.sup.+ -type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. Advantageously, the thin p+ layer used to control threshold voltage for a transfer gate of the device is extended and also used for prevention of such soft errors, thus providing reduced bulk for the device. In order to reduce bulk further, the n+-type regions (6, 7) are also reduced in thickness.

Abstract: A method for preparing a MISFET of a minute size with the channel length of not more than 2 .mu.m between a source and a drain, comprises the steps of forming a mask for exposing a region for forming a well on a planar surface of a semiconductor substrate, and introducing ions at a predetermined energy into the well region by using the mask. The predetermined energy is such as to form a peak of the impurity concentration distribution at a position deeper than the bottom surface of the source and the drain and to maintain the layer of at least a partial layer of the channel at an impurity concentration lower than 10.sup.16 cm.sup.-3 so that a high speed carrier movement in the channel is provided without causing a punch-through phenomenon.

Abstract: A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode.

Abstract: A semiconductor apparatus having a region for isolation between devices comprises a semiconductor substrate, a polycrystalline silicon layer portions selectively formed to be spaced apart from each other on the semiconductor substrate, an impurity diffused region formed under the polycrystalline silicon layer, and a silicon oxide film for filling in a space between the respective adjacent portions of the polycrystalline silicon layer. The impurity diffused region constitutes a source or drain region of a field effect device such as a MOS transistor isolated by the silicon oxide film.

Abstract: A method of manufacturing a semiconductor capacitor provided with a substrate, a dielectric film formed on the substrate and a pair of electrode layers stacked on both sides of the dielectric film comprises a step of forming a polycrystalline silicon layer for serving as one of the electrode layers on the substrate, a step of making at least a surface region of the polycrystalline silicon layer amorphous, a step of forming the dielectric film on the polycrystalline silicon layer while maintaining an amorphous surface state, and a step of forming another one of the electrode layers on the dielectric film. The lower electrode of the capacitor has its surface or the whole layer made amorphous. The surface of the electrode which is amorphous has smooth surface configuration, thereby improving the quality of the dielectric film formed thereon.

Abstract: A MOS type integrated circuit transistor includes: a channel region comprising a monocrystalline epitaxial layer; and a source/drain region of said transistor and a wiring region of a diffusion layer formed of a polycrystalline silicon layer grown on an embedded insulating film.