Abstract: A semiconductor memory device includes a trench formed along the circumference of a planar type memory capacitor, a gate insulating film and a memory cell plate being formed on the side wall of the trench, whereby the side wall of the trench is also used as a memory capacitor.At the bottom of the trench, a thick insulating film is formed to be a cell separating region.

Abstract: A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal.

Abstract: A semiconductor device and a method of manufacturing the same which comprises a semiconductor substrate and a conductive region formed thereon in multilayer structure of a film of refractory metal or refractory metal silicide inferior in corrosion resistance against a solution containing hydrofluoric acid and a film of refractory metal silicide excellent in corrosion resistance against the solution containing hydrofluorine acid and low electric resistance formed on the same.

Abstract: A semiconductor device in which a multilayer film comprising a low resistance refractory metal silicide film and a low resistance ternary alloy film formed thereon and having corrosion resistance to hydrofluoric acid is used as an electrode and interconnection. The above stated low resistance refractory metal silicide is titanium silicide or tantalum silicide. The above stated ternary alloy is titanium-M-silicon or tantalum-M-silicon, M being any of molybdenum, tungsten, niobium, vanadium and tantalum.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming memory cell portions (2, 4, 6, 11) on a p.sup.- -type semiconductor substrate (1), forming a gate insulator film (5) and a gate electrode (3) each having a larger width, by approximately 1 .mu.m, than the original width, ion-implanting p-type impurities utilizing the gate insulator film (5) and the gate electrode (3) as masks, to form p.sup.+ -type regions (120, 121), etching the side walls of the gate insulator film (5) and the gate electrode (3) to the original width and then, ion-implanting n-type impurities utilizing these regions as a mask, to form n.sup.+ -type regions (80, 81), and heat-treating these regions (80, 81, 120, 121), to form regions (80a, 81a, 120a, 121a). The p.sup.+ -type regions (120a, 121a) prevent passage of electrons out of electron-hole pairs induced by alpha rays, to prevent occurrence of soft errors. The p.sup.+ -type regions (120a, 121a) are located inside the n.sup.

Abstract: A process for preparing a semiconductor device having a walled emitter structure covering at least one side surface with a dielectric layer for separation of devices comprises a step of forming a base by implantation of ions with a resist mask for base; a step of forming an emitter by implantation of ions from an emitter-opening part; and a step of formation an active base in a base just below said emitter by implantation of ions from said emitter-opening part.