Patents by Inventor Katsumi Kishino

Katsumi Kishino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200044418
    Abstract: Alight emitting device includes a substrate, and a stacked body provided to the substrate, and including a columnar part aggregate constituted by p columnar parts, wherein the stacked body includes a plurality of the columnar part aggregates, the p columnar parts each have a light emitting layer, a diagram configured by respective centers of the plurality of columnar parts has rotation symmetry when viewed from a stacking direction of the stacked body, a diametrical size of q columnar parts out of the p columnar parts is different from a diametrical size of r columnar parts out of the p columnar parts, a shape of the columnar part aggregate is not rotation symmetry, the p is an integer not less than 2, the q is an integer not less than 1 and less than the p, and the r is an integer satisfying r=p?q.
    Type: Application
    Filed: August 5, 2019
    Publication date: February 6, 2020
    Inventors: Hiroki NISHIOKA, Katsumi KISHINO
  • Publication number: 20200036163
    Abstract: A light emitting apparatus including a plurality of first light emitters and a plurality of second light emitters that differ from the first light emitters in terms of resonance wavelength, in which the second light emitters are each disposed between each adjacent pair of the first light emitters, first light that resonates in the plurality of first light emitters is in phase, and second light that resonates in the plurality of second light emitters is in phase.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 30, 2020
    Applicants: Seiko Epson Corporation, Sophia School Corporation
    Inventors: Hiroki Nishioka, Katsumi Kishino
  • Publication number: 20190267775
    Abstract: A light-emitting device includes a substrate and a stack provided on the substrate. The stack includes a plurality of columnar portions each of which includes a first columnar portion and a second columnar portion which has a diameter smaller than a diameter of the first columnar portions. Each first columnar portion is provided between the substrate and the second columnar portions, and includes: a first semiconductor layer; a second semiconductor layer having a conductivity type different from a conductivity type of the first semiconductor layer; and a light-emitting layer provided between the first semiconductor layer and the second semiconductor layer and capable of generating light. The first semiconductor layer is provided between the substrate and the light-emitting layer. Each second columnar portion includes a third semiconductor layer having a conductivity type different from a conductivity type of the first semiconductor layer.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 29, 2019
    Inventors: Takafumi NODA, Katsumi KISHINO
  • Patent number: 9680058
    Abstract: A group-III nitride structure includes a substrate 102 and a fine wall-shaped structure 110 disposed to stand on the substrate 102 in a vertical direction relative to a surface of the substrate 102 and extending in an in-plane direction of the substrate 102. The fine wall-shaped structure 110 contains a group-III nitride semiconductor crystal, and h is larger than d assuming that the height of the fine wall-shaped structure 110 is h and the width of the fine wall-shaped structure 110 in a direction perpendicular to the height direction and the extending direction is d.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: June 13, 2017
    Assignee: SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Akihiko Kikuchi
  • Publication number: 20160254138
    Abstract: A method of manufacturing a semiconductor element by forming, on a substrate, columnar crystals of a nitride-base or an oxide-base compound semiconductor, and by using the columnar crystals, wherein on the surface of the substrate, the columnar crystals are grown while ensuring anisotropy in the direction of c-axis, by controlling ratio of supply of Group-III atoms and nitrogen, or Group-II atoms and oxygen atoms, and temperature of crystal growth, so as to suppress crystal growth in the lateral direction on the surface of the substrate.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 1, 2016
    Applicant: SOPHIA SCHOOL CORPORATION
    Inventors: Akihiko KIKUCHI, Katsumi KISHINO
  • Patent number: 9362717
    Abstract: A method of manufacturing a semiconductor element by forming, on a substrate, columnar crystals of a nitride-base or an oxide-base compound semiconductor, and by using the columnar crystals, wherein on the surface of the substrate, the columnar crystals are grown while ensuring anisotropy in the direction of c-axis, by controlling ratio of supply of Group-III atoms and nitrogen, or Group-II atoms and oxygen atoms, and temperature of crystal growth, so as to suppress crystal growth in the lateral direction on the surface of the substrate.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 7, 2016
    Assignee: SOPHIA SCHOOL CORPORATION
    Inventors: Akihiko Kikuchi, Katsumi Kishino
  • Patent number: 9224595
    Abstract: The present invention provides a semiconductor optical element array including: a semiconductor substrate having a main surface in which a plurality of concave portions is formed; a mask pattern that is formed on the main surface of the semiconductor substrate and includes a plurality of opening portions provided immediately above the plurality of concave portions; a plurality of fine columnar crystals that is made of a group-III nitride semiconductor grown from the plurality of concave portions to the upper side of the mask pattern through the plurality of opening portions; an active layer that is grown on each of the plurality of fine columnar crystals; and a semiconductor layer covering each of the active layers.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: December 29, 2015
    Assignee: SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Akihiko Kikuchi, Hiroto Sekiguchi
  • Patent number: 8896100
    Abstract: A III nitride structure includes a film 108 having a surface composed of a metal formed in a predetermined region on the surface of a substrate 102, and a fine columnar crystal 110 composed of at least a III nitride semiconductor formed on the surface of the substrate 102, wherein the spatial occupancy ratio of the fine columnar crystal 110 is higher on the surface of the substrate 102 where the film 108 is not formed than that on the film.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 25, 2014
    Assignee: Sophia School Corporation
    Inventors: Katsumi Kishino, Akihiko Kikuchi
  • Patent number: 8050305
    Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0?x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0?x6<1, x4+x5+x6=1).
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: November 1, 2011
    Assignees: Sony Corporation, Hitachi, Ltd., Sophia School Corporation
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Publication number: 20110169025
    Abstract: The present invention provides a semiconductor optical element array including: a semiconductor substrate having a main surface in which a plurality of concave portions is formed; a mask pattern that is formed on the main surface of the semiconductor substrate and includes a plurality of opening portions provided immediately above the plurality of concave portions; a plurality of fine columnar crystals that is made of a group-III nitride semiconductor grown from the plurality of concave portions to the upper side of the mask pattern through the plurality of opening portions; an active layer that is grown on each of the plurality of fine columnar crystals; and a semiconductor layer covering each of the active layers.
    Type: Application
    Filed: August 27, 2009
    Publication date: July 14, 2011
    Applicant: SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Akihiko Kikuchi, Hiroto Sekiguchi
  • Patent number: 7899104
    Abstract: An n-type cladding layer structure which has good luminescence properties without the use of substances corresponding to RoHS Directive and a high Cl-doping efficiency, i.e. which facilitates the manufacture of a semiconductor optical element and device with low crystal defects and high reliability, and an active layer and a p-type cladding layer therefor are provided. The n-type layer being lattice matched to an InP substrate and containing Group II-VI compound as a main ingredient is a Group II-VI compound semiconductor, in which the Group II elements consist of Mg, Zn, and Be and the Group VI elements consist of Se and Te. The n-type layer of the present invention is characterized by a large energy gap, high energy of the bottom of a conduction band that is effective for suppressing the Type II luminescence, high carrier concentration, and low crystal defects attributed to a good quality crystallinity.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: March 1, 2011
    Assignees: Hitachi, Ltd., Sophia School Corporation, Sony Corporation
    Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Kunihiko Tasai, Koshi Tamamura, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Publication number: 20100252836
    Abstract: A group-III nitride structure includes a substrate 102 and a fine wall-shaped structure 110 disposed to stand on the substrate 102 in a vertical direction relative to a surface of the substrate 102 and extending in an in-plane direction of the substrate 102. The fine wall-shaped structure 110 contains a group-III nitride semiconductor crystal, and h is larger than d assuming that the height of the fine wall-shaped structure 110 is h and the width of the fine wall-shaped structure 110 in a direction perpendicular to the height direction and the extending direction is d.
    Type: Application
    Filed: November 26, 2008
    Publication date: October 7, 2010
    Applicant: Sophia School Corporation
    Inventors: Katsumi Kishino, Akihiko Kikuchi
  • Patent number: 7772586
    Abstract: The present invention aims at providing a structure in which a high p-type carrier concentration of 1×1017 cm?3 or more is obtained in a material in which, although it shows normally p-type conductivity, a carrier concentration smaller than 1×1017 cm?3 is only obtained. Also, the present invention aims at providing highly reliable semiconductor element and device each of which has excellent characteristics such as light emitting characteristics and a long lifetime. Each specific layer, i.e., each ZnSe0.53Te0.47 layer (2 ML) is inserted between host layers, i.e., Mg0.5Zn0.29Cd0.21Se layers (each having 10 ML (atomic layer) thickness) each of which is lattice matched to an InP substrate. In this case, each specific layer in which a sufficient carrier concentration of 1×1018 cm?3 or more is obtained when a single layer is inserted at suitable intervals.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: August 10, 2010
    Assignees: Sophia School Corporation, Sony Corporation, Hitachi, Ltd.
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Hitoshi Nakamura
  • Publication number: 20100193910
    Abstract: A III nitride structure includes a film 108 having a surface composed of a metal formed in a predetermined region on the surface of a substrate 102, and a fine columnar crystal 110 composed of at least a III nitride semiconductor formed on the surface of the substrate 102, wherein the spatial occupancy ratio of the fine columnar crystal 110 is higher on the surface of the substrate 102 where the film 108 is not formed than that on the film.
    Type: Application
    Filed: August 27, 2008
    Publication date: August 5, 2010
    Applicant: SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Akihiko Kikuchi
  • Patent number: 7668217
    Abstract: The present invention provides a Be-based group II-VI semiconductor laser using an InP substrate and having a stacked structure capable of continuous oscillation at a room temperature. A basic structure of a semiconductor laser is constituted by using a Be-containing lattice-matched II-VI semiconductor above an InP substrate. An active laser, an optical guide layer, and a cladding layer are constituted in a double hetero structure having a type I band line-up in order to enhance the injection efficiency of carriers to the active layer. Also, the active layer, the optical guide layer, and the cladding layer, which are capable of enhancing the optical confinement to the active layer, are constituted, and the cladding layer is constituted with bulk crystals.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 23, 2010
    Assignees: Hitachi, Ltd., Sophia School Corporation, Sony Corporation
    Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Hitoshi Nakamura, Tsukuru Ohtoshi, Takeshi Kikawa, Sumiko Fujisaki, Shigehisa Tanaka
  • Publication number: 20100040103
    Abstract: The present invention provides a semiconductor device including: a semiconductor layer including an n-type first cladding layer, an n-type second cladding layer, an active layer, a p-type first cladding layer, and a p-type second cladding layer in this order on an InP substrate. The n-type first cladding layer and the n-type second cladding layer satisfy formulas (1) to (4) below, or the p-type first cladding layer and the p-type second cladding layer satisfy formulas (5) to (8) below.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 18, 2010
    Applicants: HITACHI, LTD, SOPHIA SCHOOL CORPORATION, SONY CORPORATION
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Patent number: 7656918
    Abstract: A semiconductor laser having an n-cladding layer, an optical guide layer, an active layer, an optical guide layer, and a p-cladding layer above an InP substrate, in which the active layer has a layer constituted with Be-containing group II-VI compound semiconductor mixed crystals, and at least one of layers of the n-cladding layer, the optical guide layer, and the p-cladding layer has a layer constituted with elements identical with those of the Be-containing group II-VI compound semiconductor mixed crystals of the active layer, and the layer is constituted with a superlattice structure comprising, as a well layer, mixed crystals of a Be compositions with the fluctuation of the composition being within ±30% compared with the Be composition of the group II-VI compound semiconductor mixed crystals of the active layer, whereby the device characteristics of the semiconductor laser comprising the Be-containing group II-VI compound semiconductor matched with the InP substrate.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: February 2, 2010
    Assignees: Hitachi, Ltd., Sophia School Corporation, Sony Corporation
    Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Hitoshi Nakamura
  • Publication number: 20090141763
    Abstract: There is disclosed a Be-containing II-VI group semiconductor laser that has a laminated structure formed on an InP substrate to continuously emit at room temperature without crystal degradation. A basic structure of the semiconductor laser is formed over the InP substrate by use of a lattice-matched II-VI group semiconductor including Be. An active layer and cladding layers are formed to be a double heterostructure with a type I band lineup, in order to increase the efficiency for injecting carriers into the active layer. The active layer and the cladding layers are also formed to enhance the light confinement to the active layer, in which the Mg composition of the p-type cladding layer is set to Mg<0.2.
    Type: Application
    Filed: February 27, 2008
    Publication date: June 4, 2009
    Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Sumiko Fujisaki, Hitoshi Nakamura, Takeshi Kikawa, Shigehisa Tanaka
  • Publication number: 20090059985
    Abstract: An n-type cladding layer structure which has good luminescence properties without the use of substances corresponding to RoHS Directive and a high Cl-doping efficiency, i.e. which facilitates the manufacture of a semiconductor optical element and device with low crystal defects and high reliability, and an active layer and a p-type cladding layer therefor are provided. The n-type layer being lattice matched to an InP substrate and containing Group II-VI compound as a main ingredient is a Group II-VI compound semiconductor, in which the Group II elements consist of Mg, Zn, and Be and the Group VI elements consist of Se and Te. The n-type layer of the present invention is characterized by a large energy gap, high energy of the bottom of a conduction band that is effective for suppress the Type II luminescence, high carrier concentration, and low crystal defects attributed to a good quality crystallinity.
    Type: Application
    Filed: February 27, 2008
    Publication date: March 5, 2009
    Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Kunihiko Tasai, Koshi Tamamura, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Publication number: 20080298415
    Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0<x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0<x6<1, x4+x5+x6=1).
    Type: Application
    Filed: June 3, 2008
    Publication date: December 4, 2008
    Applicants: SONY CORPORATION, HITACHI, LTD, SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa