Patents by Inventor Katsumi Nakamura

Katsumi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6364005
    Abstract: Tanks of a first heat exchanger have plane sections perpendicular to bottoms having a plurality of tube insertion holes formed therein. Tanks of a second heat exchanger with circular cross sections have bottoms having a plurality of tube insertion holes formed therein. The axes of the tube insertion holes of the first and second heat exchangers are held in parallel with each other. The second heat exchanger is in contact with the plane sections of the first heat exchanger tank.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: April 2, 2002
    Assignee: Calsonic Kansei Corporation
    Inventors: Kenji Makino, Hiroyasu Koizumi, Minoru Tsuchiya, Kunio Matsugi, Hiroshi Chikuma, Satoshi Ishihara, Makoto Tajima, Yoshiki Tsuda, Toshiaki Yamamoto, Hideki Kobayashi, Katsumi Nakamura, Junichi Enari, Mamoru Baba
  • Publication number: 20010045566
    Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
    Type: Application
    Filed: May 23, 2001
    Publication date: November 29, 2001
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
  • Publication number: 20010042885
    Abstract: In a trenched MOS gate power device having a trenched MOS gate structure, a gate insulating film is formed on the walls of trenches to extend onto a major surface of a semiconductor substrate, and gates are formed so as to fill up the trenches and to extend onto the gate insulating film on the major surface of the semiconductor substrate. The gate insulating film is formed so that the thickness of a portion thereof formed on the major surface of the semiconductor substrate is greater than that of a portion thereof formed on the walls of the trenches to narrow portions of the gates corresponding to the tops of the trenches. Thus, the characteristics of a gate insulating film formed on the walls of trenches are improved.
    Type: Application
    Filed: January 14, 1998
    Publication date: November 22, 2001
    Inventor: KATSUMI NAKAMURA
  • Patent number: 6265735
    Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: July 24, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
  • Publication number: 20010006836
    Abstract: There is disclosed a method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.
    Type: Application
    Filed: May 11, 2000
    Publication date: July 5, 2001
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Patent number: 6218217
    Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: April 17, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akio Uenishi, Katsumi Nakamura
  • Patent number: 6199622
    Abstract: A connecting structure for connecting a radiator having a reinforcement member and a condenser having a bracket is provided. The structure includes a connecting member having a spacer portion and a holding portion integrally formed on opposite sides of a notch. The spacer portion is fittingly inserted into the reinforcement member, and a folded portion of the reinforcement member and the condenser bracket are inserted into the notch. A bolt is inserted through the reinforcement member, the spacer portion, the bracket and the holding portion and a nut is screwed onto a tip of the bolt for clamping the radiator and the condenser together.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: March 13, 2001
    Assignee: Calsonic Kansei Corporation
    Inventors: Katsuji Mashio, Fumihiro Inoue, Yukinobu Take, Hiroshi Koizumi, Katsumi Nakamura, Hironori Muramoto
  • Patent number: 6173766
    Abstract: An integrated heat exchanger includes a radiator having a core formed between a pair of radiator tanks, a condenser adjoining the radiator and having the core formed between a pair of condenser tanks, and a corrugated fin provided in the core and shared between the radiator and the condenser, the heat exchanger containing first partitions which divide the inside of the pair of condenser tanks to thereby create fluid chambers on one side of the respective condenser tanks in such a way as to become opposite to each other; and a fluid inflow pipe and a fluid outflow pipe connected to the fluid chamber of the condenser tanks.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: January 16, 2001
    Assignee: Calsonic Kansei Corporation
    Inventors: Katsumi Nakamura, Michitake Sumida
  • Patent number: 6167953
    Abstract: A cylindrical tank body is formed by folding a plate material which has a brazing filler metal layer and is formed from aluminum clad. One end of the plate material is extended along the other end of the tank body, and the thus-extended portion is brazed to the end.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: January 2, 2001
    Assignee: Calsonic Corporation
    Inventors: Hideki Kobayashi, Katsumi Nakamura, Kenji Makino
  • Patent number: 6117734
    Abstract: A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: September 12, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsumi Nakamura
  • Patent number: 6111290
    Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.- silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: August 29, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akio Uenishi, Katsumi Nakamura
  • Patent number: 6095239
    Abstract: Tanks of a first heat exchanger have plane sections perpendicular to bottoms having a plurality of tube insertion holes formed therein. Tanks of a second heat exchanger with circular cross sections have bottoms having a plurality of tube insertion holes formed therein. The axes of the tube insertion holes of the first and second heat exchangers are held in parallel with each other. The second heat exchanger is in contact with the plane sections of the first heat exchanger tank.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: August 1, 2000
    Assignee: Calsonic Kansei Corporation
    Inventors: Kenji Makino, Hiroyasu Koizumi, Minoru Tsuchiya, Kunio Matsugi, Hiroshi Chikuma, Satoshi Ishihara, Makoto Tajima, Yoshiki Tsuda, Toshiaki Yamamoto, Hideki Kobayashi, Katsumi Nakamura, Junichi Enari, Mamoru Baba
  • Patent number: 6029348
    Abstract: An oil cooler mounting structure includes: a heat exchanger tank main body that is made of aluminum and has an oil cooler mounting hole in a wall surface thereof; an oil cooler that is made of aluminum, has an insertion hole for an oil introducing/discharging pipe formed in a seat portion, and is mounted inside the heat exchanger tank with a plurality of projecting pieces erected around the circumference of the insertion hole; a patch that is made of an aluminum-containing brazing filler metal and is arranged on the outer circumference of the projecting pieces of the oil cooler; and the oil introducing/discharging pipe that is inserted into the insertion hole formed in the seat portion of the oil cooler.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: February 29, 2000
    Assignee: Calsonic Corporation
    Inventors: Kenji Makino, Haruo Ikeda, Hiroyasu Koizumi, Hideki Kobayashi, Katsumi Nakamura
  • Patent number: 5977570
    Abstract: A pin diode is formed by a p.sup.+ collector region, an n type buffer region, an n.sup.- region and an n.sup.+ cathode region. A trench is formed from the surface of n.sup.+ cathode region through n.sup.+ cathode region to reach n.sup.- region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n.sup.+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n.sup.+ cathode region. An anode electrode is formed to be electrically connected to p.sup.+ collector region. The n.sup.+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: November 2, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
  • Patent number: 5937938
    Abstract: An oil cooler mounting structure includes: a heat exchanger tank main body that is made of aluminum and has an oil cooler mounting hole in a wall surface thereof; an oil cooler that is made of aluminum, has an insertion hole for an oil introducing/discharging pipe formed in a seat portion, and is mounted inside the heat exchanger tank with a plurality of projecting pieces erected around the circumference of the insertion hole; a patch that is made of an aluminum-containing brazing filler metal and is arranged on the outer circumference of the projecting pieces of the oil cooler; and the oil introducing/discharging pipe that is inserted into the insertion hole formed in the seat portion of the oil cooler.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: August 17, 1999
    Assignee: Calsonic Corporation
    Inventors: Kenji Makino, Haruo Ikeda, Hiroyasu Koizumi, Hideki Kobayashi, Katsumi Nakamura
  • Patent number: 5894149
    Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.31 silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: April 13, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akio Uenishi, Katsumi Nakamura
  • Patent number: 5875836
    Abstract: A structure for attaching a fan shroud so as to cover a core formed between a pair of tanks which are spaced a given distance away from and opposite to each other, the structure including a guide groove formed integrally in a tank body belonging to each of the pair of tanks; and guides which are formed on both sides of the fan shroud facing the pair of tanks, respectively.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: March 2, 1999
    Assignee: Calsonic Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 5783491
    Abstract: A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: July 21, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsumi Nakamura, Tadaharu Minato, Shuuichi Tominaga, Katsuomi Shiozawa
  • Patent number: 5698730
    Abstract: A cyanoacetic acid higher ester represented by the general formula: NCCH.sub.2 COOR', wherein R' represents an alkyl group having 4 to 20 carbon atoms, is prepared by subjecting a cyanoacetic acid ester represented by the general formula: NCCH.sub.2 COOR.sup.1, wherein R.sup.1 represents an alkyl group having 1 to 3 carbon atom, to a transesterification with an alcohol represented by the general formula: R'OH, wherein R' represents an alkyl group having 4 to 20 carbon atoms, in the presence of a specific tin compound as the catalyst. According to the present invention, the cyanoacetic acid higher esters which are useful as intermediates for pharmaceuticals and agricultural chemicals as well as intermediates for industrial products can be prepared easily and in higher yield as compared with conventional methods, by using a cyanoacetic acid ester and an alcohol which are less expensive and easily available as raw materials.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: December 16, 1997
    Assignee: Nitto Chemical Industry Co., Ltd.
    Inventors: Katsumi Nakamura, Yasuyuki Takayanagi, Masaaki Seya
  • Patent number: 5661332
    Abstract: A diffused resistor capable of suppressing variation of characteristics caused by leakage of current occurring under high-temperature conditions. An N-type layer is epitaxially grown on a P-type substrate, and an N-type resistor island isolated by a P-type isolation region is formed. A P-type diffused resistor is formed in the island. An N-type region of high impurity concentration is disposed in close proximity to the high-potential end of the P-type diffused resistor. An electrode is brought into contact with not only the high-potential end but also the N-type high-impurity concentration region through the same contact hole. Thus, a parasitic transistor, which is formed from the P-type diffused resistor, the N-type resistor island and the P-type substrate (P-type isolation region), can be prevented from turning on with a minimal increase of the element area.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: August 26, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Katsumi Nakamura, Tomohisa Yamamoto, Hiroyuki Ban