Abstract: A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench may extend from the main surface to the substrate and have an inner wall covered with an insulating film. At least one of an edge on the side of the substrate and an edge on the side opposite thereof of the semiconductor layer has a rounded surface. Further, an angle between a line tangent to a surface having a smallest radius of curvature of the rounded surface of the edge and the main surface ranges from 30° to 60° at a section of the edge.

Abstract: A flow rate control valve 1 comprises a first sleeve 4 and a second sleeve 5 fitted into an inner periphery of a housing 3. The both sleeves 4 and 5 have inner end faces 4d and 5d which are disposed in abutment against each other while being displaced from each other radially, thereby forming annular stepped end faces 4d? and 5d? on a common plane. An edge of the stepped end faces define a first seat S1. The valve body 6 has an outer peripheral surface which is formed as a beveled surface, which defines a second seat S2. The second seat S2 of the valve body 6 is disposed in linear contact with the first seat S1 to close a flow path in a gas passage 2. With this arrangement, a seal leakage when a butterfly valve 7 is closed can be reduced in comparison to the prior art.

Abstract: A gate electrode <13> is provided to fill up a trench <300> while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode <13> located upward beyond a P-type base layer <4> and an N+-type emitter diffusion layer <51>, WT represents the diameter (sectional width) of an inner wall of a linearly extending portion of the trench <300> and WC represents the distance between the boundary (the inner wall of the trench 300) between a gate oxide film <11> and the P-type base layer <4> and an end surface of the gate electrode <13> located upward beyond the trench <300> in a section of the trench <300>, relation of either WG?1.3·WT or WC?0.2 ?m holds between these dimensions.

Abstract: A gate electrode <13> is provided to fill up a trench <300> while covering its opening. Assuming that WG represents the diameter (sectional width) of a head portion of the gate electrode <13> located upward beyond a P-type base layer <4> and an N+-type emitter diffusion layer <51>, WT represents the diameter (sectional width) of an inner wall of a linearly extending portion of the trench <300> and WC represents the distance between the boundary (the inner wall of the trench 300) between a gate oxide film <11> and the P-type base layer <4> and an end surface of the gate electrode <13> located upward beyond the trench <300> in a section of the trench <300>, relation of either WG?1.3·WT or WC?0.2 ?m holds between these dimensions.

Abstract: A flow rate control valve 1 comprises a first sleeve 4 and a second sleeve 5 fitted into an inner periphery of a housing 3. The both sleeves 4 and 5 have inner end faces 4d and 5d which are disposed in abutment against each other while being displaced from each other radially, thereby forming annular stepped end faces 4d? and 5d? on a common plane. An edge of the stepped end faces define a first seat S1. The valve body 6 has an outer peripheral surface which is formed as a beveled surface, which defines a second seat S2. The second seat S2 of the valve body 6 is disposed in linear contact with the first seat S1 to close a flow path in a gas passage 2. With this arrangement, a seal leakage when a butterfly valve 7 is closed can be reduced in comparison to the prior art.

Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).

Abstract: The present invention provides a method and apparatus of recycling a printed circuit board for separating and retrieving a metallic material, which includes a printed metallic material, and an insulating material, both composing the printed circuit board. Both the metallic material and the insulating material, which are separated and retrieved, are possible for recycling. In the method for recycling the printed circuit board, hot filtration equipment 4a and resin-metal separation equipment 51 are used in hot filtration process P400. The waste printed circuit board 1 is heated and force-filtered so that only the insulating material 1a pass through the filter. Then, the insulating material 1a and the metallic material 1b are separated and retrieved. It is preferred that the insulating body base 23 of the printed circuit board 100 as the waste printed circuit board is made of thermoplastic resin or a mixture of thermoplastic resin and inorganic loading material.

Abstract: A semiconductor device of the present invention has an insulating gate type field effect transistor portion having an n-type emitter region (3) and an n? silicon substrate (1), which are opposed to each other sandwiching a p-type body region (2), as well as a gate electrode (5a) which is opposed to p-type body region (2) sandwiching a gate insulating film (4a), and also has a stabilizing plate (5b). This stabilizing plate (5b) is made of a conductor or a semiconductor, is opposed to n? silicon substrate (1) sandwiching an insulating film (4, 4b) for a plate, and forms together with n? silicon substrate (1), a capacitor. This stabilizing plate capacitor formed between stabilizing plate (5b) and n? silicon substrate (1) has a capacitance greater than that of the gate-drain capacitor formed between gate electrode (5a) and n? silicon substrate (1).

Abstract: A core structure of a heat exchanger includes seat plates arranged opposite to each other with a predetermined space interposed between them and formed with tube holes, reinforcements connecting the seat plates at their end portions, tubes fixed at its both end portions by insertion into the tube holes, corrugated fins arranged between the tubes, and an upper and lower tanks attached to the seat plates. The tanks are connected by the tubes so that coolant flows between the tanks through the tubes. Tubes arranged at outermost positions of a core part among the tubes are inserted at its end portions by insert members so that the insert members can increase rigidity of the end positions of the outermost positioned tubes and ensure flowing of the coolant between the tanks through the outermost positioned tubes.

Abstract: A semiconductor device of the present invention includes an MOSFET which has a stacked gate insulation film formed of at least two types of insulation films, that is, a thermal oxide film provided on a semiconductor substrate and a CVD oxide film provided nearer to a gate electrode than thermal oxide film. The stacked insulation film is provided so that the ratio of the thickness of the CVD oxide film to that of the entire stacked gate insulation film is at least 20%. By such a structure, the gate insulation film thickness is kept uniform. Further, nitrogen may be segregated at an interface between the thermal oxide film and a semiconductor substrate and an interface between the gate electrode and the CVD oxide film. Thus, the occurrence of interface states is prevented between the gate insulation film and the semiconductor substrate as well as between the gate insulation film and the gate electrode.

Abstract: A member used within a plasma processing apparatus and exposed to a plasma of a halogen gas such as BCl3 or Cl2 is formed from a sintered body of metals of Group IIIa of Periodic Table such as Y, La, Ce, Nd and Dy, and Al and/or Si, for example, 3Y2O3.5Al2O3, 2Y2O3.Al2O3, Y2O3.Al2O3 or disilicate or monosilicate, and in particular, in this sintered body, the content of impurity metals of Group IIa of Periodic Table contained in the sintered body is controlled to be 0.15 wt % or more in total. Specifically, for this member, an yttrium-aluminum-garnet sintered body having a porosity of 3% or less and also having a surface roughness of 1 ?m or less in center line average roughness Ra is utilized.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A semiconductor device of the present invention includes an MOSFET which has a stacked gate insulation film formed of at least two types of insulation films, that is, a thermal oxide film provided on a semiconductor substrate and a CVD oxide film provided nearer to a gate electrode than thermal oxide film. The stacked insulation film is provided so that the ratio of the thickness of the CVD oxide film to that of the entire stacked gate insulation film is at least 20%. By such a structure, the gate insulation film thickness is kept uniform. Further, nitrogen may be segregated at an interface between the thermal oxide film and a semiconductor substrate and an interface between the gate electrode and the CVD oxide film. Thus, the occurrence of interface states is prevented between the gate insulation film and the semiconductor substrate as well as between the gate insulation film and the gate electrode.

Abstract: Tanks of a first heat exchanger have plane sections perpendicular to bottoms having a plurality of tube insertion holes formed therein. Tanks of a second heat exchanger with circular cross sections have bottoms having a plurality of tube insertion holes formed therein. The axes of the tube insertion holes of the first and second heat exchangers are held in parallel with each other. The second heat exchanger is in contact with the plane sections of the first heat exchanger tank.

Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: A semiconductor device of the present invention is provided with a power device which has a semiconductor substrate having a first main surface and a second main surface that are opposed to each other and an insulating gate structure on the first main surface side, wherein a main current flows between the first main surface and the second main surface, that is to say, is provided with an insulating gate type MOS transistor structure wherein the thickness (t1) of the semiconductor substrate is no less than 50 ?m and no greater than 250 ?m and a low ON voltage and a high withstanding capacity against breakdown are implemented in the first main surface. Thereby, a low ON voltage, the maintaining of the withstanding capacity against breakdown and the reduction of a switching loss on the high voltage side can be implemented.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A semiconductor device of the present invention includes an MOSFET which has a stacked gate insulation film formed of at least two types of insulation films, that is, a thermal oxide film provided on a semiconductor substrate and a CVD oxide film provided nearer to a gate electrode than thermal oxide film. The stacked insulation film is provided so that the ratio of the thickness of the CVD oxide film to that of the entire stacked gate insulation film is at least 20%. By such a structure, the gate insulation film thickness is kept uniform. Further, nitrogen may be segregated at an interface between the thermal oxide film and a semiconductor substrate and an interface between the gate electrode and the CVD oxide film. Thus, the occurrence of interface states is prevented between the gate insulation film and the semiconductor substrate as well as between the gate insulation film and the gate electrode.

Abstract: Tanks of a first heat exchanger have plane sections perpendicular to bottoms having a plurality of tube insertion holes formed therein. Tanks of a second heat exchanger with circular cross sections have bottoms having a plurality of tube insertion holes formed therein. The axes of the tube insertion holes of the first and second heat exchangers are held in parallel with each other. The second heat exchanger is in contact with the plane sections of the first heat exchanger tank.