Patents by Inventor Katsumi Okawa

Katsumi Okawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9892997
    Abstract: A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of the semiconductor package and configured to provide a first electrical connection to at least one terminal of the at least one semiconductor device, a second at least one lead protruding from a second side of the semiconductor package and configured to provide a second electrical connection to the at least one terminal of the at least one semiconductor device, and a continuous conductive structure configured to provide a conductive path between the first at least one lead, the second at least one lead, and the at least one terminal of the at least one semiconductor device through the leadframe island such that the at least one semiconductor device continues to function after trimming the first at least one lead.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: February 13, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Heny Lin, Katsumi Okawa
  • Publication number: 20170301613
    Abstract: A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of the semiconductor package and configured to provide a first electrical connection to at least one terminal of the at least one semiconductor device, a second at least one lead protruding from a second side of the semiconductor package and configured to provide a second electrical connection to the at least one terminal of the at least one semiconductor device, and a continuous conductive structure configured to provide a conductive path between the first at least one lead, the second at least one lead, and the at least one terminal of the at least one semiconductor device through the leadframe island such that the at least one semiconductor device continues to function after trimming the first at least one lead.
    Type: Application
    Filed: April 19, 2016
    Publication date: October 19, 2017
    Inventors: Heny Lin, Katsumi Okawa
  • Patent number: 7609498
    Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select one
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: October 27, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
  • Patent number: 7276793
    Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: October 2, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 7220921
    Abstract: In the present invention there is formed a sheet-like board member 50 having conductive coating films, such as first pads 55 and die pads 59, formed thereon or a sheet-like board member 50 which has been half-etched by using conductive coating films such as first pads 55 and die pads 59. A hybrid IC can be manufactured by means of utilization of post-processing processes of a semiconductor manufacturer. Further, a hybrid IC can be manufactured without adoption of a support board, and hence there can be manufactured a hybrid IC which is of lower profile and has superior heat dissipation characteristics.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: May 22, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 7173336
    Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 6, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Publication number: 20070014065
    Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select one
    Type: Application
    Filed: September 19, 2006
    Publication date: January 18, 2007
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
  • Patent number: 7138296
    Abstract: A method of manufacturing a semiconductor device is described. A board that includes a flat back face, corresponding to a resin sealing area, and a front face that has projections is provided. The projections are formed of a metal that is integral with the board and include (a) a bonding pad provided in an area surrounded by an area that contacts an upper die, (b) a wiring that is integrated with the bonding pad and which extends to a semiconductor element mounting area, and (c) an electrode provided in one body with the wiring. A semiconductor element is mounted on the semiconductor element area and electrically connected to the bonding pad. The board is placed on a lower die and resin is filled into a space formed by the board and upper die. The board is divided into multiple devices such that the projections are separated by removing the board exposed at the back face of the resin.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: November 21, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 7136269
    Abstract: An inverter circuit overcurrent protection device in which an overcurrent detection resistor (Rs) is incorporated in a hybrid integrated circuit, in which a detection voltage from the overcurrent detection resistor (Rs) is divided by voltage dividing resistors (R1 and R2) and is compared with a reference voltage in an overcurrent detection circuit, for carrying out an overcurrent protection, and an external resistor is connected in series or in parallel with one of the voltage dividing resistors (R1 and R2) to change a division ratio so that the level of overcurrent protection can be adjusted; and an embodiment wherein, in the vicinity of a current detection terminal, a first pad (P1) is connected to a detection voltage from the overcurrent detection resistance, a second pad (P2) is connected to a detection voltage from the amplifier, and a third pad (P3) is connected to the voltage dividing resistors, and a bonding wire (10) is connected between the current detection terminal one of said pads, to select one
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: November 14, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
  • Patent number: 7125798
    Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: October 24, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 7091606
    Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: August 15, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 7075762
    Abstract: In order to enable overheat protection and overcurrent protection as well as temperature detection of an inverter circuit, an inverter circuit comprises a switching circuit 9 composed of a plurality of switching elements and a control circuit 1 for generating a control signal to be inputted into a drive circuit 2 to control a load, a temperature detecting element 12 for detecting a change in temperature of the inverter circuit is provided in a temperature detection circuit 10, and a temperature detection signal which changes according to a change in temperature of said inverter circuit, an overheat abnormal signal outputted upon a rise in temperature to a predetermined temperature or more, and an overcurrent abnormal signal outputted from an overcurrent protection FET 13 are outputted via one commonly used terminal.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 11, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
  • Publication number: 20060033209
    Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 16, 2006
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
  • Patent number: 6975024
    Abstract: In a manufacturing method of a hybrid integrated circuit device of the invention, transfer molding is carried put by positioning a curved surface formed in a back surface of the substrate on a lower mold die side and a burr formed in a main surface of the substrate on an upper mold die side. This utilizes the curved surface to inject thermosetting resin in an arrow direction to pour the thermosetting resin through a below of the substrate. There are no broken fragments of burr in a thermosetting resin at the below of the substrate. As a result, a required minimum resin thickness is secured at the below of the substrate, thus realizing a hybrid integrated circuit device having a high voltage resistance, an excellent heat dissipation property and a high product quality.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 13, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Koike, Hidefumi Saito, Katsumi Okawa, Junichi Iimura
  • Patent number: 6975022
    Abstract: A device containing a flat member is provided, having a pattern for a bonding pad, a wiring, and an electrode, by half-etching through the flat member.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 13, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 6974727
    Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: December 13, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Hidefumi Saito
  • Publication number: 20050146052
    Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.
    Type: Application
    Filed: February 8, 2005
    Publication date: July 7, 2005
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Publication number: 20050056916
    Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.
    Type: Application
    Filed: August 13, 2004
    Publication date: March 17, 2005
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Publication number: 20040214374
    Abstract: By forming a flat member 10 forming a conductive film 11 having substantially same pattern with a second bonding pad 17, a wiring 18, and an electrode 19 for taking out , or forming a flat member 30 half-etched through the conductive film 11, it is possible to manufacture a semiconductor device 23 of BGA structure using a back process of a semiconductor maker.
    Type: Application
    Filed: May 26, 2004
    Publication date: October 28, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
  • Patent number: 6756610
    Abstract: A light irradiating device (68) having the good radiation characteristic comprises a plurality of conductive paths (51) that are electrically separated, a photo semiconductor chips (65) fixed onto desired conductive path (51), and a resin (67) for covering the photo semiconductor chips (65) to support the conductive paths (51) integrally.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: June 29, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Kouji Takahashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa