Patents by Inventor Katsunori Nishii
Katsunori Nishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040113158Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.Type: ApplicationFiled: September 2, 2003Publication date: June 17, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kaoru INOUE, Katsunori NISHII, Hiroyuki MASATO
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Patent number: 6737683Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.Type: GrantFiled: February 25, 2003Date of Patent: May 18, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
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Publication number: 20040061194Abstract: A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.Type: ApplicationFiled: June 3, 2003Publication date: April 1, 2004Inventors: Yoshito Ikeda, Kaoru Inoue, Yutaka Hirose, Katsunori Nishii
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Publication number: 20030222276Abstract: An active region formed of a Group III nitride semiconductor is formed on a substrate. Then, an electrode is formed on the active region and a protective insulating film is formed on a part of the active region located in the peripheral portion of the electrode by oxidizing the Group III nitride semiconductor.Type: ApplicationFiled: May 14, 2003Publication date: December 4, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Katsunori Nishii, Yoshito Ikeda, Kaoru Inoue
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Patent number: 6653714Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills thType: GrantFiled: November 20, 2002Date of Patent: November 25, 2003Assignee: Matsushita Electronics Corp.Inventors: Toshinobu Matsuno, Takeshi Fukuda, Katsunori Nishii, Kaoru Inoue, Daisuke Ueda
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Publication number: 20030209762Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.Type: ApplicationFiled: June 9, 2003Publication date: November 13, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
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Publication number: 20030205721Abstract: The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.Type: ApplicationFiled: March 21, 2001Publication date: November 6, 2003Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
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Patent number: 6639255Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.Type: GrantFiled: December 8, 2000Date of Patent: October 28, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
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Publication number: 20030160265Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.Type: ApplicationFiled: February 26, 2003Publication date: August 28, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
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Publication number: 20030160269Abstract: A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.Type: ApplicationFiled: February 25, 2003Publication date: August 28, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kaoru Inoue, Yoshito Ikeda, Yutaka Hirose, Katsunori Nishii
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Patent number: 6593193Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.Type: GrantFiled: January 25, 2002Date of Patent: July 15, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
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Publication number: 20030107101Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.Type: ApplicationFiled: December 27, 2002Publication date: June 12, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
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Publication number: 20030109088Abstract: The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.Type: ApplicationFiled: December 20, 2002Publication date: June 12, 2003Applicant: Matsushita Electronics CorporationInventors: Katsunori Nishii, Yoshito Ikeda, Hiroyuki Masato, Kaoru Inoue
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Publication number: 20030096478Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills thType: ApplicationFiled: November 20, 2002Publication date: May 22, 2003Inventors: Toshinobu Matsuno, Takeshi Fukuda, Katsunori Nishii, Kaoru Inoue, Daisuke Ueda
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Patent number: 6531718Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.Type: GrantFiled: January 12, 2001Date of Patent: March 11, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
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Patent number: 6503808Abstract: A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a bass region; a lower portion of the second semiconductor region which at least fills thType: GrantFiled: October 13, 2000Date of Patent: January 7, 2003Assignee: Matsushita Electronics CorporationInventors: Toshinobu Matsuno, Takeshi Fukuda, Katsunori Nishii, Kaoru Inoue, Daisuke Ueda
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Publication number: 20020119610Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.Type: ApplicationFiled: January 25, 2002Publication date: August 29, 2002Inventors: Katsunori Nishii, Kaoru Inoue, Toshinobu Matsuno, Yoshito Ikeda, Hiroyuki Masato
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Publication number: 20020022330Abstract: An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.Type: ApplicationFiled: October 30, 2001Publication date: February 21, 2002Inventors: Takeshi Fukuda, Daisuke Ueda, Kaoru Inoue, Katsunori Nishii, Toshinobu Matsuno
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Patent number: 6323538Abstract: An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.Type: GrantFiled: January 11, 2000Date of Patent: November 27, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Fukuda, Daisuke Ueda, Kaoru Inoue, Katsunori Nishii, Toshinobu Matsuno
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Publication number: 20010020700Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.Type: ApplicationFiled: January 12, 2001Publication date: September 13, 2001Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato