Patents by Inventor Katsunori Nishii

Katsunori Nishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010015446
    Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
    Type: Application
    Filed: December 8, 2000
    Publication date: August 23, 2001
    Inventors: kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
  • Patent number: 6153499
    Abstract: A first resist film for EB exposure, a buffer film, and a second resist film for i-line exposure are applied sequentially onto a substrate. Thereafter, the second resist film and the buffer film are subjected to patterning for forming a first opening. Then, dry etching is performed with respect to the first resist film masked with the second resist film to transfer the pattern of the second resist film to the first resist film and thereby form a second opening in the first resist film. Subsequently, a third resist film of chemically amplified type is applied to the entire surface of the first resist film to form a mixing layer in conjunction with the first resist film. As a result, the wall faces of the second opening are covered with the mixing layer and the width of the second opening is thereby reduced.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: November 28, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiharu Anda, Toshinobu Matsuno, Katsunori Nishii, Kaoru Inoue, Manabu Yanagihara, Mitsuru Tanabe
  • Patent number: 5942772
    Abstract: A heterojunction epitaxial layer, including a first semiconductor layer containing Al and having a thickness of 50 nm or less and a second semiconductor layer different in composition from the first semiconductor layer, is formed on a substrate composed of semi-insulating GaAs. A gate electrode is formed on a specified region of the top surface of the heterojunction epitaxial layer. The source/drain formation regions of the heterojunction epitaxial layer are provided with respective high-concentration N-type impurity diffusion regions, on which respective ohmic electrodes are formed.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: August 24, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsunori Nishii, Mitsuru Nishitsuji, Takahiro Yokoyama, Akiyoshi Tamura
  • Patent number: 5872393
    Abstract: In fabricating an MFIC by mounting a semiconductor chip on a substrate having a microstrip line by MBB bonding, a benzocyclobutene (BCB) film is used as a dielectric film of the microstrip line. By providing a means for preventing the deformation, peeling, and cracking of the BCB film during the fabrication process, the thickness of the dielectric film is held substantially equal even after flip-chip mounting, which reduces impedance fluctuations.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: February 16, 1999
    Assignees: Matsushita Electric Industrial Co., Ltd., Matsushita Electronics Corporation
    Inventors: Hiroyuki Sakai, Takayuki Yoshida, Yorito Ohta, Kaoru Inoue, Katsunori Nishii, Yoshito Ikeda
  • Patent number: 5585655
    Abstract: On a semi-insulating substrate is formed a conductive layer and an undoped layer. On specified regions of the conductive layer are formed ohmic electrodes, each serving as a source electrode or a drain electrode, via a pair of square contact regions. The circumferential edges of the contact regions are undercut beneath the ohmic electrodes. Between the pair of contact regions on the conductive layer is formed a gate electrode by self alignment using the ohmic electrodes as a mask. The gate electrode has extended in the direction of gate width and the extended portion serves as a withdrawn portion of the gate electrode. Upper electrodes are formed by self alignment in the same process in which the gate electrode is formed.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: December 17, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yorito Ota, Katsunori Nishii, Mitsuru Nishitsuji, Hiroyuki Masato, Hiromasa Fujimoto
  • Patent number: 5370973
    Abstract: A fine structure T-shaped electrode is fabricated using a phase shift method. A photoresist layer is formed on a semiconductor substrate and the photoresist layer is exposed to an exposure light having a first wavelength through a photomask which has a desired pattern of a base shifting layer whereby the phase of the exposure light is shifted by 180 degrees. The photoresist layer is then exposed to another exposure light having a second wavelength that is different from the first wavelength through the photomask. The photoresist is developed to form a T-shaped resist cavity and a metal layer is deposited over the resist layer formed on the semiconductor substrate. All the metal layer is removed except for the areas covering the T-shaped photoresist pattern. The T-shaped electrode is also formed by disposing a photoresist layer on a semiconductor substrate.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: December 6, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Katsunori Nishii