Patents by Inventor Katsunori Ueno

Katsunori Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140169045
    Abstract: Provided is a longitudinal bidirectional device in which current flows in a layering direction of a semiconductor layered portion formed on a front surface of a substrate, the bidirectional device comprising a first semiconductor element that includes a first channel and is formed on the semiconductor layered portion; and a second semiconductor element that includes a second channel and is provided on the substrate side of the first semiconductor element within the semiconductor layered portion. The first semiconductor element further includes a first control electrode that controls the first channel and that is formed on a surface of the semiconductor layered portion that faces away from the substrate, and the second semiconductor element is formed on at least a portion of the surface of the semiconductor layered portion on which the first control electrode is formed and includes a second control electrode that controls the second channel.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Katsunori UENO
  • Publication number: 20130292699
    Abstract: The present invention prevents breakage of a gate insulating film of a MOS device and provides a nitride semiconductor device having improved reliability. An SBD metal electrode provided between a drain electrode and a gate electrode is configured to form a Schottky junction with an AlGaN layer. Further, the SBD metal electrode and a source electrode are connected and electrically short-circuited. Consequently, when an off signal is inputted to the gate electrode, a MOSFET part is turned off and the drain-side voltage of the MOSFET part becomes close to the drain electrode voltage. When the drain electrode voltage increases, the SBD metal electrode voltage becomes lower than the drain-side voltage of the MOSFET part, thus the drain side of the MOSFET part and the drain electrode are electrically disconnected by the SBD metal electrode.
    Type: Application
    Filed: October 26, 2011
    Publication date: November 7, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Katsunori Ueno, Shusuke Kaya
  • Publication number: 20130043485
    Abstract: A p-type GaN-based semiconductor device is provided. Porivded is a GaN-based semiconductor device including: a first channel layer which is formed from a GaN-based semiconductor, and in which a carrier gas of a first conductivity type occurs; a barrier layer formed on the first channel layer from a GaN-based semiconductor having a higher bandgap than the first channel layer; and a second channel layer which is formed on the barrier layer from a GaN-based semiconductor having a lower bandgap than the barrier layer, and in which a carrier gas of a second conductivity type occurs, wherein the carrier concentration of the carrier gas of the second conductivity type is lower in a region below a first gate electrode than in other regions between a first source electrode and a first drain electrode, and is controlled by the first gate electrode.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventor: Katsunori UENO
  • Publication number: 20130032819
    Abstract: The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.
    Type: Application
    Filed: March 2, 2011
    Publication date: February 7, 2013
    Applicants: TOHOKU UNIVERISTY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi Kambayashi, Katsunori Ueno, Takehiko Nomura, Yoshihiro Sato, Akinobu Teramoto, Tadahiro Ohmi
  • Publication number: 20120298875
    Abstract: In a radiation measurement apparatus, an analog pulse signal output from a semiconductor radiation detector is converted to a plurality of digital signals by an analog-to-digital converter for each analog pulse signal. A threshold circuit for inputting these digital signals discriminates digital signals exceeding a threshold value. A digital signal integration circuit integrates the plurality of discriminated digital signals for each analog pulse signal and obtains an integrated value for each analog pulse signal. A spectrum generation circuit for inputting the respective integrated values generates a radiation energy spectrum using the integrated values and accurately performs the quantitative analysis and energy analysis of a radioactive nuclide using the radiation energy spectrum. A quantitative analysis and an energy analysis of a radioactive nuclide can be accurately performed while a time resolution of a radiation detector can be maintained.
    Type: Application
    Filed: April 26, 2012
    Publication date: November 29, 2012
    Applicant: Hitachi, Ltd.
    Inventors: Katsunori UENO, Takahiro Tadokoro, Hiroshi Kitaguchi, Mizuho Tsuyuki, Nobuyuki Ota, Makoto Nagase
  • Patent number: 8283697
    Abstract: An internal combustion engine igniter semiconductor device is disclosed which is low cost yet secures energy withstand and reverse surge withstand capability. An IGBT includes a clamping diode between a collector electrode and a gate electrode. The IGBT has two n-type buffer layers of differing impurity concentrations between a p+ substrate and an n-type base layer of the IGBT, wherein the total thickness of the two-layer buffer layer is 50 ?m or less, and the overall impurity amount is 20×1013 cm?2 or less.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8269594
    Abstract: An insulated transformer, which can suppress aging deterioration and can reduce the influence of noise caused by external magnetic flux, while improving reliability and environmental resistance, and can send and receive signals while electrically insulating a low-voltage side and a high-voltage side. A secondary coil is formed on a semiconductor substrate, and a primary coil is formed on one face of a glass substrate. The primary coil fixes the glass substrate formed on one face onto the semiconductor substrate through the other face of the glass substrate by an adhesive layer.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: September 18, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroyuki Yoshimura, Katsunori Ueno, Masaharu Edo
  • Publication number: 20120134459
    Abstract: A gamma scanning apparatus includes a moving and fixing mechanism which moves/fixes a housing to a definite position, and a rotating and moving mechanism which moves a fuel assembly vertically in addition to rotating the assembly. A gamma-ray counting circuit measures an output of a gamma-ray detector, and a data collecting/analyzing and controlling apparatus analyzes data output from the gamma-ray counting circuit, in association with data relating to the rotation and movement of the fuel assembly by the rotating and moving mechanism. The rotating and moving mechanism, after fixing the vertical position of the fuel assembly with the housing also fixed, rotates the fuel assembly through 360° with its height kept constant, and during the 360° rotation of the fuel assembly, the gamma-ray counting circuit measures either a time average of count values of the detector during the rotation or an integral value within a fixed time.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 31, 2012
    Inventors: Takahiro TADOKORO, Hiroshi Kitaguchi, Katsunori Ueno, Yutaka Iwata, Ryusuke Kimura
  • Publication number: 20120104261
    Abstract: A fuel assembly radiation measuring apparatus has a radiation signal generation apparatus including a LaBr3(Ce) scintillator, an A/D converter, a signal processing apparatus, and a data analysis apparatus. The signal processing apparatus has a FPGA and a CPU. ? rays emitted from a fuel assembly disposed in water in a fuel pool enter into the LaBr3(Ce) scintillator that emits scintillator light, then a photomultiplier tube converts the light into an electric signal as a radiation detection signal. A pulse height analyzer of the FPGA inputs a radiation detection signal having a digital waveform generated by the A/D converter and changes the digital waveform into a trapezoid waveform to obtain a maximum peak value. The data analysis apparatus quantifies a target nuclide using a plurality of inputted maximum peak values to obtain burnup.
    Type: Application
    Filed: October 25, 2011
    Publication date: May 3, 2012
    Inventors: Hiroshi Kitaguchi, Takahiro Tadokoro, Katsunori Ueno, Yutaka Iwata, Ryusuke Kimura
  • Patent number: 8039879
    Abstract: A semiconductor has an IGBT active section and a control circuit section for detecting an IGBT abnormal state. A collector region is formed on the back surface side (i.e., on the IGBT collector side) in a selective manner, namely right under the IGBT active section.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: October 18, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8039346
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n? semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n+ first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 18, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 7994890
    Abstract: An insulating transformer includes a semiconductor substrate, an insulating substrate, a primary winding provided on one of the semiconductor substrate and the insulating substrate, a secondary winding provided on other of the semiconductor substrate and the insulating substrate, and an insulating spacer layer provided in between the semiconductor substrate and the insulating substrate for insulating and separating the primary winding and the secondary winding. The primary winding and the secondary winding are disposed to face each other. The insulating spacer layer maintains a constant interval between the semiconductor substrate and the insulating substrate.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: August 9, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Masaharu Edo, Katsunori Ueno, Hiroyuki Yoshimura
  • Patent number: 7982524
    Abstract: A level shift circuit and a semiconductor device are configured to prevent failure and malfunction even when an excessive negative voltage or ESD surge are applied to a high-voltage power supply terminal. The level shift circuit includes a level shift resistor, a current-limiting resistor connected in series to the level shift resistor, and an n-channel MOSFET, with its drain connected to the current-limiting resistor. An output of the level-up circuit is obtained from the positioned between the level shift resistor and the current-limiting resistor. By providing the current-limiting resistor, the current that flows due to an excessive negative voltage or ESD surge is suppressed to prevent the level shift circuit from failing or malfunctioning.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 19, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yuichi Harada, Yoshihiro Ikura, Yasumasa Watanabe, Katsunori Ueno
  • Publication number: 20110133246
    Abstract: An internal combustion engine igniter semiconductor device is disclosed which is low cost yet secures energy withstand and reverse surge withstand capability. An IGBT includes a clamping diode between a collector electrode and a gate electrode. The IGBT has two n-type buffer layers of differing impurity concentrations between a p+ substrate and an n-type base layer of the IGBT, wherein the total thickness of the two-layer buffer layer is 50 ?m or less, and the overall impurity amount is 20×1013 cm?2 or less.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 9, 2011
    Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.
    Inventor: Katsunori UENO
  • Patent number: 7947600
    Abstract: A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film is deposited on the whole face of a semiconductor substrate having an impurity-diffused region. This insulating film is partially removed to form a first opening and a second opening. A primary coil is formed such that a center pad contacts the impurity-diffused region through the first opening. A thin insulating film is deposited on the primary coil. An insulator material having a secondary coil formed thereon is adhered onto the insulating film on the primary coil by adhesive tape. The insulator material is sized to not cover both a pad, connected with the center pad of the primary coil through the impurity-diffused region, and an outer-end pad of the primary coil.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: May 24, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Masanobu Iwaya, Reiko Hiruta, Katsunori Ueno, Kunio Mochizuki
  • Publication number: 20100285647
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n? semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n+ first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.
    Type: Application
    Filed: July 23, 2010
    Publication date: November 11, 2010
    Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.
    Inventor: Katsunori UENO
  • Publication number: 20100270586
    Abstract: A semiconductor device having high reliability and high load short circuit withstand capability while maintaining a low ON resistance is provided, by using a WBG semiconductor as a switching element of an inverter circuit. In the semiconductor device for application to a switching element of an inverter circuit, a band gap of a semiconductor material is wider than that of silicon, a circuit that limits a current when a main transistor is short circuited is provided, and the main transistor that mainly serves to pass a current, a sensing transistor that is connected in parallel to the main transistor and detects a microcurrent proportional to a current flowing in the main transistor, and a lateral MOSFET that controls a gate of the main transistor on the basis of an output of the sensing transistor are formed on the same semiconductor.
    Type: Application
    Filed: March 5, 2010
    Publication date: October 28, 2010
    Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.
    Inventor: Katsunori UENO
  • Patent number: 7791135
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n? semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n+ first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: September 7, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Katsunori Ueno
  • Publication number: 20100109015
    Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.
    Type: Application
    Filed: September 4, 2009
    Publication date: May 6, 2010
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventor: Katsunori UENO
  • Patent number: 7700971
    Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance. The device combines a static induction transistor structure with an insulated gate field effect transistor structure. The advantages of both the SIT structure and the insulated gate field effect transistor structure are obtained. The structures are formed on the same SiC semiconductor substrate, with the MOSFET structure above the SIT structure. The SIT structure includes a p+ gate region in an n-type drift layer on an n+ SiC semiconductor substrate, and an n+ first source region on the surface of the drift layer. The MOSFET structure includes a p-well region on the surface of the first source region, a second source region formed in the p-well region, and a MOS gate structure formed in a trench extending from the second source region to the first source region. The p+ gate region and a source electrode are conductively connected.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: April 20, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventor: Katsunori Ueno