Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

Abstract: A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other.

Abstract: A silicon carbide vertical field-effect transistor is provided wherein a first conductivity type drift layer formed of silicon carbide is laminated on a first conductivity type silicon carbide drain layer, and a second conductivity type gate region and a first conductivity type source region are formed in selected portions of a surface layer of the first conductivity type drift layer, such that the gate and source regions are spaced from each other, while a second conductivity type embedded region is formed in a selected portion of the drift layer below the gate region and source region, such that the embedded region is not connected to the source region. A second conductivity type contact region that is in contact with the embedded region is short-circuited to a gate electrode that is formed on the gate region, so that the potential of the embedded region is made equal to that of the gate region. A method for manufacturing such a silicon carbide vertical FET is also disclosed.

Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.

Abstract: In a method for manufacturing a silicon carbide semiconductor device, preliminary heat treatment is conducted after implanting impurity ions into a silicon carbide substrate, such that the silicon carbide substrate is heated at a temperature in a range of, for example, 800 to 1200° C., in a hydrogen atmosphere or a mixed gas ambient comprising hydrogen and inert gas. After the preliminary heat treatment, the silicon carbide substrate may be annealed at a high temperature.

Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

Abstract: To increase the rate or speed of formation of a thermal oxide film of a silicon carbide semiconductor device, the partial pressure of water vapor is controlled to within the range of 0.1 to 0.95 when a surface of silicon carbide is oxidized under a mixed atmosphere of water vapor and oxygen. In a pyrogenic oxidation method in which hydrogen and oxygen are introduced to perform thermal oxidation, the ratio of the flow rate of hydrogen to that of oxygen is controlled to within the range of 1:0.55 to 1:9.5. In another pyrogenic oxidation method in which hydrogen and oxygen are introduced to perform thermal oxidation, a large portion of an oxide film is formed while the ratio of the flow rate of hydrogen to that of oxygen is controlled to about 1:4.5, and a remaining portion of the oxide film is then formed while the ratio of the flow rate of hydrogen to that of oxygen is controlled to about 1:0.55.

Abstract: A method for manufacturing a SiC semiconductor device is provided in which a first conductivity type source region is formed by implanting impurity ions, using a mask provided by a pattern of an oxide film formed by thermally oxidizing a patterned polysilicon film, and a second-conductivity type base region is formed by implanting impurity ions, using a mask provided by a pattern of a polysilicon film from which the above oxide film is removed. Since the edge of the mask for forming the base region is located behind that of the mask for forming the source region due to the oxidation process, the second conductivity type base region and first conductivity type source region provide self-aligned impurity regions with uniform channel regions. Also, a polysilicon film that provides a gate electrode layer of the semiconductor device is subjected to thermal oxidation, so that the resulting oxide film provides an interlayer insulating film on the gate electrode layer.

Abstract: In a method for forming a thermal oxide film of a silicon carbide semiconductor device, a preliminary treatment is conducted in which a silicon carbide substrate is heated to 800 to 1200.degree. C., in an atmosphere comprising hydrogen or a mixture of hydrogen and inert gas, and then a silicon dioxide film is formed on the substrate by thermal oxidation. A slight amount of hydrochloric acid gas may be added to the atmosphere for the preliminary treatment.

Abstract: In a method for forming a silicon carbide vertical FET, a first mask and a second mask that overlaps the first mask are used so that a first conductivity type impurity region is defined by one end of a certain portion of the first mask, and that portion of the first mask and the second mask are then removed so that a second conductivity type impurity region is defined by another portion of the first mask. Thus, the first conductivity type impurity region and the second conductivity type impurity region are positioned relative to each other, with respect to the first mask. If a mask including a tapered end portion is used, and ion implantation is conducted with different accelerating-field voltages, the first conductivity type region and the second conductivity type region may be formed by self-alignment, using only one mask. By controlling the impurity concentration of the channel region, the threshold voltage can be controlled, and a normally-off type FET can be provided.

Abstract: A method for manufacturing a silicon carbide semiconductor device having pn junctions is provided wherein a recessed portion is formed in a certain pattern in a surface of a substrate formed of a silicon carbide crystal, and an epitaxial layer having a conductivity type opposite to that of the substrate is grown on the substrate, and the surface of the surface is flattened so that the pn junctions appear on the surface of the substrate.

Abstract: A method of manufacturing a silicon carbide vertical MOSFET is presented which includes: providing a first conductivity type silicon carbide substrate; a first conductivity type drift layer comprising silicon carbide which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base region formed in a selected region of a surface layer of the first conductivity type drift layer; a first conductivity type source region formed in a selected region of the second conductivity type base region; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer; a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base region; and a drain electrode formed on a rear surface of the silicon carbide substrate.

Abstract: A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent to the trench. The buried region is preferably disposed in the base layer, or between a drift layer of a second conductivity type and the base layer. The region of the first conductivity type is optionally disposed below the bottom of the trench to encourage expansion of the depletion layer of the MOSFET. A depletion-type vertical SiC MESFET of the invention includes a buried region of the first conductivity type in a base layer of a second conductivity type. A Schottky electrode on a portion of the base layer above the buried region ensures adequate expansion of a depletion layer.

Abstract: A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent to the trench. The buried region is preferably disposed in the base layer, or between a drift layer of a second conductivity type and the base layer. The region of the first conductivity type is optionally disposed below the bottom of the trench to encourage expansion of the depletion layer of the MOSFET. A depletion-type vertical SiC MESFET of the invention includes a buried region of the first conductivity type in a base layer of a second conductivity type. A Schottky electrode on a portion of the base layer above the buried region ensures adequate expansion of a depletion layer.

Abstract: An insulated-gate controlled semiconductor device includes a main circuit that is controlled by an insulated gate having a gate resistor, an overload detector having the insulated gate for use in common with the main circuit, the overload detector being of the same construction as that of the main circuit, a current detector for detecting current passing through the overload detector, and a field effect transistor having a gate which responds to the voltage drop across the current detector. The main circuit is protected by lowering the voltage applied to the insulated gate through the gate resistor and through the low on-resistance of the field effect transistor while the field effect transistor is held on.

Abstract: A Schottky electrode is formed on an n-type SiC base member with an Al--Ti alloy or by laying Al films and Ti films alternately, and a resulting structure is subjected to a heat treatment of 600.degree. C. to 1,200.degree. C. A p-type SiC layer may be formed around the Schottky junction so as to form a p-n junction with the n-type SiC base member.

Abstract: In a semiconductor device, in addition to a first emitter layer, a second emitter layer is formed on the surface side of a p-type base in spaced-apart relation with the first emitter layer. The first emitter layer is the source region of a first MOSFET, while the second emitter layer is the source region of a second MOSFET. Through signals imparted to first and second gate electrodes, the device, when turned on, operates with a low on-state voltage drop in a thyristor state and, when turned off, undergoes a turn-off in a short time by changing to a transistor state. The main current in the transistor state flows by being offset toward the first emitter layer side with respect to a main-current path on the lower side of the second emitter layer in the thyristor state. Since the current paths in each mode are separated, it is possible to reduce the resistance in the current path in the transistor state without increasing the on-voltage, thereby making it possible to obtain a large latch-up withstand capability.

Abstract: A silicon carbide trench MOSFET is provided that includes a first conductivity type semiconductor substrate made of silicon carbide. A first conductivity type drift layer and a second conductivity type base layer, both made of silicon carbide, are sequentially formed by epitaxial growth on the semiconductor substrate. The first conductivity type drift layer has a lower impurity concentration than the semiconductor substrate. A first conductivity type source region is formed in a part of a surface layer of the second conductivity type base layer. A gate electrode is received through an insulating film, in a first trench extending from a surface of the first conductivity type source region to reach the first conductivity type drift layer. A Schottky electrode disposed on an inner surface of a second trench having a greater depth than the first trench.

Abstract: A silicon carbide trench MOSFET is provided that includes a first conductivity type semiconductor substrate made of silicon carbide. A first conductivity type drift layer and a second conductivity type base layer, both made of silicon carbide, are sequentially formed by epitaxial growth on the semiconductor substrate. The first conductivity type drift layer has a lower impurity concentration than the semiconductor substrate. A first conductivity type source region is formed in a part of a surface layer of the second conductivity type base layer. A gate electrode is received through an insulating film, in a first trench extending from a surface of the first conductivity type source region to reach the first conductivity type drift layer. A Shottky electrode disposed on an inner surface of a second trench having a greater depth than the first trench.

Abstract: A semiconductor device having a thyristor structure including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type; a first MISFET capable of injecting majority carriers from the fourth semiconductor region into the second semiconductor region; and a second MISFET capable of being turned on and off independently of the first MISFET and extracting majority carriers from the third semiconductor region into the fourth semiconductor region, wherein the fourth semiconductor region is divided into the source region of the first MISFET and the source region of the second MISFET, the latter being formed in a portion isolated from the former, characterized in that the depth of the source region of the second MISFET is different from that of the drain region thereof.